Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d8e0e5aa41c12703d1bee46613abd91f0493f769..1890cc23c55ded7b9477dbc819e60f17e35950d2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,45 @@
+2023-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_): Rename to...
+       (aarch64_float_truncate_lo_<mode><vczle><vczbe>): ... This.
+
+2023-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/99195
+       * config/aarch64/aarch64-simd.md (aarch64_addp<mode>): Rename to...
+       (aarch64_addp<mode><vczle><vczbe>): ... This.
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/stormy16/stormy16.cc (xstormy16_rtx_costs): Rewrite to
+       provide reasonable values for common arithmetic operations and
+       immediate operands (in several machine modes).
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/stormy16/stormy16.cc (xstormy16_print_operand): Add %h
+       format specifier to output high_part register name of SImode reg.
+       * config/stormy16/stormy16.md (extendhisi2): New define_insn.
+       (zero_extendqihi2): Fix lengths, consistent formatting and add
+       "and Rx,#255" alternative, for documentation purposes.
+       (zero_extendhisi2): New define_insn.
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/stormy16/stormy16.cc (xstormy16_output_shift): Implement
+       SImode shifts by two by performing a single bit SImode shift twice.
+
+2023-04-23  Aldy Hernandez  <aldyh@redhat.com>
+
+       PR tree-optimization/109593
+       * value-range.cc (frange::operator==): Handle NANs.
+
+2023-04-23  liuhongt  <hongtao.liu@intel.com>
+
+       PR rtl-optimization/108707
+       * ira-costs.cc (scan_one_insn): Use NO_REGS instead of
+       GENERAL_REGS when preferred reg_class is not known.
+
 2023-04-22  Andrew Pinski  <apinski@marvell.com>
 
        * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker):

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e372b3d6ca6bde0de4b99c79f384ced3e315e6a1..b5f339e560b0fb58c55035fdfc2ec5e73b77dee8 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230423
+20230424

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 028a8bc7af8f1b2e43818106090e54f2b3fc7c2f..611be74e81a9d54c7b14641aa27be5f76d5707f9 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,43 @@
+2023-04-23  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       * lib/gm2.exp (gm2_target_compile_default): Conditionally
+       append -lnsl -lsocket to ldflags.
+
+2023-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/float_truncate_zero.c: New test.
+
+2023-04-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/99195
+       * gcc.target/aarch64/simd/pr99195_1.c: Add testing for vpadd intrinsics.
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/xstormy16/mulhi.c: New test case.
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/xstormy16/extendhisi2.c: New test case.
+       * gcc.target/xstormy16/zextendhisi2.c: Likewise.
+
+2023-04-23  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/xstormy16/shiftsi.c: New test case.
+
+2023-04-23  liuhongt  <hongtao.liu@intel.com>
+
+       * gcc.target/i386/avx2-dest-false-dep-for-glc.c: Rewrite
+       testcase to make the codegen more stable.
+       * gcc.target/i386/avx512dq-dest-false-dep-for-glc.c: Ditto
+       * gcc.target/i386/avx512f-dest-false-dep-for-glc.c: Ditto.
+       * gcc.target/i386/avx512fp16-dest-false-dep-for-glc.c: Ditto.
+       * gcc.target/i386/avx512vl-dest-false-dep-for-glc.c: Ditto.
+
+2023-04-23  liuhongt  <hongtao.liu@intel.com>
+
+       * gcc.target/i386/pr108707.c: New test.
+
 2023-04-22  Andrew Pinski  <apinski@marvell.com>
 
        * gcc.dg/tree-ssa/phi-opt-5.c: Remvoe some xfail.