i386: Refactor AVX512 comparisons in machine description sse.md.

This patch refactors/tidies up the define_insns for vector comparisons
on 512-bit vectors in sse.md.  The motivation is that the current
organization (accidentally) introduces dubious instructions such as
avx512f_cmpv16si3_mask_round and avx512vl_cmpv2di3_mask_round, which
are integer comparisons that specify a floating point rounding mode!?

The problem is caused by the decomposition of mode iterators.
Currently, sse.md uses four patterns: (1) for signed comparions
of floating point and large integer modes (V48H), (2) for signed
comparisons of small integer modes (VI12), (3) for unsigned
comparisons of small integer modes (VI12) and (4) for unsigned
comparisons of large integer modes (VI48).  The first pattern
also allows for variants specifying the FP rounding mode.

The refactoring below uses a more sensible decomposition into
only three patterns: (1) for [signed] comparisons of floating
point modes (VFH), (2) for signed comparisons of integers (VI1248)
and (3) for unsigned comparisons of integers (VI1248).

For the record, to show this produces the same coverage:

V48H = v{16,8,4}si v{8,4,2}di v{32,16,8}hf v{16,8,4}sf v{8,4,2}df
V12 = v{64,32,16}qi v{32,16,8}hi

VFH = v{32,16,8}hf v{16,8,4}sf v{8,4,2}df
VI1248 = v{64,32,16}qi v{32,16,8}hi v{16,8,4}si v{8,4,2}di

The simplification also allows a clean-up of predicates
(for operand[3]) as there are 8 integer comparison operators
and 32 floating point comparison operators, and we no longer
need cmp_imm_predicate to restrict range based upon <mode>.

V48H cmp_imm_predicate -> VFH const_0_to_31_operand (FP)
VI12 cmp_imm_predicate -> VI1248 const_0_to_7_operand (signed)
VI12 const_0_to_7_operand ->
VI48 const_0_to_7_operand -> VI1248 const_0_to_7_operand (unsigned)

There are no changes other than removing the non-sensical patterns
from insn-emit, insn-recog and friends.

2026-04-26  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/i386/sse.md
	(<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>):
	Change mode iterator from V48H_AVX512VL to VFH_AVX512VL and op3's
	predicate from <cmp_imm_predicate> to const_0_to_31_operand.
	(<avx512>_cmp<mode>3<mask_scalar_merge_name>): Change mode
	iterator from VI12_AVX512VL to VI1248_AVX512VLBW.
	(<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Likewise.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7804269acb2069a4dbe5fc0532dbb0ab00504271..40d6bd71b8f691dc34ec24c3857fb439ee5f4f49 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4611,12 +4611,13 @@
    (V16HI "const_0_to_7_operand")   (V32QI "const_0_to_7_operand")
    (V8HI "const_0_to_7_operand")    (V16QI "const_0_to_7_operand")])
 
+;; AVX512 floating point comparisons
 (define_insn "<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
        (unspec:<avx512fmaskmode>
-         [(match_operand:V48H_AVX512VL 1 "register_operand" "v")
-          (match_operand:V48H_AVX512VL 2 "nonimmediate_operand" "<round_saeonly_constraint>")
-          (match_operand:SI 3 "<cmp_imm_predicate>" "n")]
+         [(match_operand:VFH_AVX512VL 1 "register_operand" "v")
+          (match_operand:VFH_AVX512VL 2 "nonimmediate_operand" "<round_saeonly_constraint>")
+          (match_operand:SI 3 "const_0_to_31_operand" "n")]
          UNSPEC_PCMP))]
   "TARGET_AVX512F && <round_saeonly_mode512bit_condition>"
   "v<ssecmpintprefix>cmp<ssemodesuffix>\t{%3, <round_saeonly_mask_scalar_merge_op4>%2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2<round_saeonly_mask_scalar_merge_op4>, %3}"
@@ -4805,14 +4806,15 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "TI")])
 
+;; AVX512 signed integer comparisons
 (define_insn "<avx512>_cmp<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
-          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "<cmp_imm_predicate>" "n")]
+         [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+          (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")
+          (match_operand:SI 3 "const_0_to_7_operand" "n")]
          UNSPEC_PCMP))]
-  "TARGET_AVX512BW"
+  "TARGET_AVX512F"
   "vpcmp<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
   [(set_attr "type" "ssecmp")
    (set_attr "length_immediate" "1")
@@ -4940,20 +4942,6 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
-  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
-       (unspec:<avx512fmaskmode>
-         [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
-          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_7_operand")]
-         UNSPEC_UNSIGNED_PCMP))]
-  "TARGET_AVX512BW"
-  "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
-  [(set_attr "type" "ssecmp")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "evex")
-   (set_attr "mode" "<sseinsnmode>")])
-
 (define_insn "*<avx512>_ucmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>"
   [(set (match_operand:SWI248x 0 "register_operand" "=k")
        (zero_extend:SWI248x
@@ -5029,11 +5017,12 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
+;; AVX512 unsigned integer comparisons
 (define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
-          (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
+         [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v")
+          (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")
           (match_operand:SI 3 "const_0_to_7_operand")]
          UNSPEC_UNSIGNED_PCMP))]
   "TARGET_AVX512F"