rs6000: Change mode and insn condition for scalar extract sig instruction

gcc/
	* config/rs6000/rs6000-builtins.def
	(__builtin_vsx_scalar_extract_sig): Set return type to const signed
	long long.
	* config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with
	TARGET_POWERPC64.

gcc/testsuite/
	* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Replace lp64 check
	with has_arch_ppc64.
	* gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise.
	* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 6240a6ae6c051e40b33871792a67e1b05c1826e4..c396e27619cc79f24cb6517afd8eaf1697f21578 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2862,7 +2862,7 @@
   pure vsc __builtin_vsx_lxvl (const void *, signed long);
     LXVL lxvl {}
 
-  const signed long __builtin_vsx_scalar_extract_sig (double);
+  const signed long long __builtin_vsx_scalar_extract_sig (double);
     VSESDP xsxsigdp {}
 
   const double __builtin_vsx_scalar_insert_exp (unsigned long long, \

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3f3f76e711b07e7f59b44f88644b24a4d41ce3b4..3991ec3b0c0ce9bf16780c13f76d061e575de95b 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5039,7 +5039,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
         UNSPEC_VSX_SXSIG))]
-  "TARGET_P9_VECTOR && TARGET_64BIT"
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
   "xsxsigdp %0,%x1"
   [(set_attr "type" "integer")])
 

diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
index 637080652b7a7b1eec84a740fae07b05306710f1..d22f7d1b2744a0aa533f4caf06b5bf1219758901 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
 
 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>

diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
index f12eed3d9d5be052062b610cf4f0004a7659d845..64747d73a51574eb04df410c288105e1bacec2d8 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
 
 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>

diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
index c85072da1381620b00a58d59670b9e25e576cd56..561be53fb9b4df46972222a361ac4bc82e35dbd4 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
 /* { dg-require-effective-target p9vector_hw } */
 /* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
 
 /* This test should succeed only on 64-bit configurations.  */
 #include <altivec.h>