RISC-V: Add autovectorization tests for binary integer operations.

This patchs adds scan as well as execution tests for vectorized
binary integer operations.  The tests are not comprehensive as
the vector type promotions (vec_unpack, extend etc.) are not implemented
yet.  Also, vmulh, vmulhu, and vmulhsu and others are still missing.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/shift-template.h: New test.
	* gcc.target/riscv/rvv/autovec/shift-run.c: New test.
	* gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/shift-scalar-template.h: New test.
	* gcc.target/riscv/rvv/autovec/shift-scalar-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vadd-run-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vadd-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vand-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vand-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vdiv-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vdiv-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vmax-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmax-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vmin-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmin-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vmul-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vmul-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vor-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vor-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vrem-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vrem-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vsub-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vsub-template.h: New test.
	* gcc.target/riscv/rvv/autovec/vxor-run.c: New test.
	* gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: New test.
	* gcc.target/riscv/rvv/autovec/vxor-template.h: New test.

Co-authored-by: Michael Collison <collison@rivosinc.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c
new file mode 100644 (file)
index 0000000..67e9f8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c
@@ -0,0 +1,52 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-template.h"
+
+#include <stdio.h>
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                                  \
+  TYPE a##TYPE[SZ];                                    \
+  TYPE b##TYPE[SZ];                                    \
+  for (int i = 0; i < SZ; i++)                         \
+  {                                                    \
+    a##TYPE[i] = VAL;                                  \
+    b##TYPE[i] = i % 4;                                \
+  }                                                    \
+  vshl_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);         \
+  for (int i = 0; i < SZ; i++)                         \
+    assert (a##TYPE[i] == (VAL << (i % 4)));
+
+#define RUN2(TYPE,VAL)                                 \
+  TYPE as##TYPE[SZ];                                   \
+  TYPE bs##TYPE[SZ];                                   \
+  for (int i = 0; i < SZ; i++)                         \
+  {                                                    \
+    as##TYPE[i] = VAL;                                 \
+    bs##TYPE[i] = i % 4;                               \
+  }                                                    \
+  vshiftr_##TYPE (as##TYPE, as##TYPE, bs##TYPE, SZ);   \
+  for (int i = 0; i < SZ; i++)                         \
+    assert (as##TYPE[i] == (VAL >> (i % 4)));
+
+#define RUN_ALL()      \
+ RUN(int16_t, 1)       \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, 3)       \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, 5)       \
+ RUN(uint64_t, 6)       \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c
new file mode 100644 (file)
index 0000000..da0f79a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-template.h"
+
+/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
+   Therefore, expect only 4 vsll.vv instead of 6 for now.  */
+
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c
new file mode 100644 (file)
index 0000000..aba9c84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-template.h"
+
+/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
+   Therefore, expect only 4 vsll.vv instead of 6 for now.  */
+
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c
new file mode 100644 (file)
index 0000000..1e80174
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-scalar-template.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c
new file mode 100644 (file)
index 0000000..8850d38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-scalar-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c
new file mode 100644 (file)
index 0000000..aabd2e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "shift-scalar-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h
new file mode 100644 (file)
index 0000000..a0ddc00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h
@@ -0,0 +1,119 @@
+/* Test shifts by scalar (immediate or register) amount.  */
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */
+
+#include <stdint.h>
+#include <assert.h>
+
+#define SHIFTL(TYPE,VAL)                               \
+  __attribute__ ((noipa))                               \
+  void vsll_##TYPE_##VAL (TYPE *dst, int n)            \
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] <<= VAL;                                  \
+  }
+
+#define SHIFTR(TYPE,VAL)                               \
+  __attribute__ ((noipa))                               \
+  void vsrx_##TYPE_##VAL (TYPE *dst, int n)            \
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] >>= VAL;                                  \
+  }
+
+#define TEST_ALL()     \
+SHIFTL(uint32_t,1)     \
+SHIFTL(uint32_t,2)     \
+SHIFTL(uint32_t,3)     \
+SHIFTL(uint32_t,4)      \
+SHIFTL(uint32_t,5)      \
+SHIFTL(uint32_t,6)      \
+SHIFTL(uint32_t,7)     \
+SHIFTL(uint32_t,8)     \
+SHIFTL(uint32_t,9)     \
+SHIFTL(uint32_t,10)    \
+SHIFTL(uint32_t,11)    \
+SHIFTL(uint32_t,12)    \
+SHIFTL(uint32_t,13)    \
+SHIFTL(uint32_t,14)    \
+SHIFTL(uint32_t,15)    \
+SHIFTL(uint32_t,16)    \
+SHIFTL(uint32_t,17)    \
+SHIFTL(uint32_t,18)    \
+SHIFTL(uint32_t,19)    \
+SHIFTL(uint32_t,20)    \
+SHIFTL(uint32_t,21)    \
+SHIFTL(uint32_t,22)    \
+SHIFTL(uint32_t,23)    \
+SHIFTL(uint32_t,24)    \
+SHIFTL(uint32_t,25)    \
+SHIFTL(uint32_t,26)    \
+SHIFTL(uint32_t,27)    \
+SHIFTL(uint32_t,28)    \
+SHIFTL(uint32_t,29)    \
+SHIFTL(uint32_t,30)    \
+SHIFTL(uint64_t,31)    \
+
+TEST_ALL()
+
+#define SZ 32
+
+#define TEST_VSLL(TYPE,VAL)            \
+  TYPE a##TYPE##VAL[SZ];               \
+  for (int i = 0; i < SZ; i++)         \
+    a##TYPE##VAL[i] = 2;               \
+  vsll_##TYPE_##VAL (a##TYPE##VAL, SZ);        \
+  for (int i = 0; i < SZ; i++)         \
+    assert (a##TYPE##VAL[i] == (2ll << VAL));
+
+__attribute__((noipa))
+void vsllvx (uint32_t *dst, int val, int n)
+{
+  for (int i = 0; i < n; i++)
+    dst[i] <<= val;
+}
+
+#define TEST_VSLLVX            \
+  uint32_t a[SZ];              \
+  for (int i = 0; i < SZ; i++)         \
+    a[i] = 2;          \
+  vsllvx (a, 17, SZ);  \
+  for (int i = 0; i < SZ; i++)         \
+    assert (a[i] == (2 << 17));
+
+int main ()
+{
+  TEST_VSLL(uint32_t,1)
+  TEST_VSLL(uint32_t,2)
+  TEST_VSLL(uint32_t,3)
+  TEST_VSLL(uint32_t,4)
+  TEST_VSLL(uint32_t,5)
+  TEST_VSLL(uint32_t,6)
+  TEST_VSLL(uint32_t,7)
+  TEST_VSLL(uint32_t,8)
+  TEST_VSLL(uint32_t,9)
+  TEST_VSLL(uint32_t,10)
+  TEST_VSLL(uint32_t,11)
+  TEST_VSLL(uint32_t,12)
+  TEST_VSLL(uint32_t,13)
+  TEST_VSLL(uint32_t,14)
+  TEST_VSLL(uint32_t,15)
+  TEST_VSLL(uint32_t,16)
+  TEST_VSLL(uint32_t,17)
+  TEST_VSLL(uint32_t,18)
+  TEST_VSLL(uint32_t,19)
+  TEST_VSLL(uint32_t,20)
+  TEST_VSLL(uint32_t,21)
+  TEST_VSLL(uint32_t,22)
+  TEST_VSLL(uint32_t,23)
+  TEST_VSLL(uint32_t,24)
+  TEST_VSLL(uint32_t,25)
+  TEST_VSLL(uint32_t,26)
+  TEST_VSLL(uint32_t,27)
+  TEST_VSLL(uint32_t,28)
+  TEST_VSLL(uint32_t,29)
+  TEST_VSLL(uint32_t,30)
+  TEST_VSLL(uint64_t,31)
+
+  TEST_VSLLVX
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h
new file mode 100644 (file)
index 0000000..64e0a38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST1_TYPE(TYPE)                                       \
+  __attribute__((noipa))                                       \
+  void vshl_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)                \
+  {                                                            \
+    for (int i = 0; i < n; i++)                                        \
+      dst[i] = a[i] << b[i];                                   \
+  }
+
+#define TEST2_TYPE(TYPE)                                       \
+  __attribute__((noipa))                                       \
+  void vshiftr_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)     \
+  {                                                            \
+    for (int i = 0; i < n; i++)                                        \
+      dst[i] = a[i] >> b[i];                                   \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST1_TYPE(int16_t)   \
+ TEST1_TYPE(uint16_t)  \
+ TEST1_TYPE(int32_t)   \
+ TEST1_TYPE(uint32_t)  \
+ TEST1_TYPE(int64_t)   \
+ TEST1_TYPE(uint64_t)   \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c
new file mode 100644 (file)
index 0000000..8bdc7a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c
@@ -0,0 +1,69 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vadd-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 0;                            \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 0;                           \
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == VAL);
+
+#define RUN3(TYPE,VAL)                         \
+  TYPE ai##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    ai##TYPE[i] = VAL;                         \
+  vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ);       \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (ai##TYPE[i] == VAL + 15);
+
+#define RUN3M(TYPE,VAL)                                \
+  TYPE aim##TYPE[SZ];                          \
+  for (int i = 0; i < SZ; i++)                 \
+    aim##TYPE[i] = VAL;                                \
+  vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ);    \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (aim##TYPE[i] == VAL - 16);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)    \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)   \
+ RUN3M(int16_t, 13)    \
+ RUN3(uint16_t, 14)    \
+ RUN3M(int32_t, 15)    \
+ RUN3(uint32_t, 16)    \
+ RUN3M(int64_t, 17)    \
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c
new file mode 100644 (file)
index 0000000..799ed27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vadd-template.h"
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c
new file mode 100644 (file)
index 0000000..d9ba5a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vadd-template.h"
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h
new file mode 100644 (file)
index 0000000..5ed7932
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] + b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] + b;                               \
+  }
+
+#define TEST3_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vaddi_##TYPE (TYPE *dst, TYPE *a, int n)                \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] + 15;                              \
+  }
+
+#define TEST3M_TYPE(TYPE)                              \
+  __attribute__((noipa))                               \
+  void vaddim_##TYPE (TYPE *dst, TYPE *a, int n)       \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] - 16;                              \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)  \
+ TEST3_TYPE(uint16_t)  \
+ TEST3M_TYPE(int32_t)  \
+ TEST3_TYPE(uint32_t)  \
+ TEST3M_TYPE(int64_t)  \
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c
new file mode 100644 (file)
index 0000000..1c7def5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c
@@ -0,0 +1,69 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vand-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 123;                          \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vand_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == (TYPE)(123 & VAL));
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 123;                         \
+  vands_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == (123 & VAL));
+
+#define RUN3(TYPE,VAL)                         \
+  TYPE ai##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    ai##TYPE[i] = VAL;                         \
+  vandi_##TYPE (ai##TYPE, ai##TYPE, SZ);       \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (ai##TYPE[i] == (VAL & 15));
+
+#define RUN3M(TYPE,VAL)                                \
+  TYPE aim##TYPE[SZ];                          \
+  for (int i = 0; i < SZ; i++)                 \
+    aim##TYPE[i] = VAL;                                \
+  vandim_##TYPE (aim##TYPE, aim##TYPE, SZ);    \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (aim##TYPE[i] == (VAL & -16));
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)    \
+ RUN3M(int16_t, 13)    \
+ RUN3(uint16_t, 14)    \
+ RUN3M(int32_t, 15)    \
+ RUN3(uint32_t, 16)    \
+ RUN3M(int64_t, 17)    \
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c
new file mode 100644 (file)
index 0000000..24fc70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vand-template.h"
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c
new file mode 100644 (file)
index 0000000..3cd766b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vand-template.h"
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h
new file mode 100644 (file)
index 0000000..7d02c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] & b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vands_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] & b;                               \
+  }
+
+#define TEST3_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vandi_##TYPE (TYPE *dst, TYPE *a, int n)                \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] & 15;                              \
+  }
+
+#define TEST3M_TYPE(TYPE)                              \
+  __attribute__((noipa))                               \
+  void vandim_##TYPE (TYPE *dst, TYPE *a, int n)       \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] & -16;                             \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)  \
+ TEST3_TYPE(uint16_t)  \
+ TEST3M_TYPE(int32_t)  \
+ TEST3_TYPE(uint32_t)  \
+ TEST3M_TYPE(int64_t)  \
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c
new file mode 100644 (file)
index 0000000..c8f4ce8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vdiv-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = VAL * 3;                      \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 3);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = VAL * 5;                     \
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 5);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c
new file mode 100644 (file)
index 0000000..9759401
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vdiv-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vdiv.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c
new file mode 100644 (file)
index 0000000..40fdfbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vdiv-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vdiv.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h
new file mode 100644 (file)
index 0000000..7fbba7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] / b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] / b;                               \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c
new file mode 100644 (file)
index 0000000..90e5c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmax-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 0;                            \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vmax_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 0;                           \
+  vmaxs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c
new file mode 100644 (file)
index 0000000..46a3212
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmax-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c
new file mode 100644 (file)
index 0000000..0349630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmax-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h
new file mode 100644 (file)
index 0000000..df0f9f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] > b[i] ? a[i] : b[i];              \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vmaxs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] > b ? a[i] : b;                    \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c
new file mode 100644 (file)
index 0000000..34f9348
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmin-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 0;                            \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vmin_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 0;                           \
+  vmins_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)    \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c
new file mode 100644 (file)
index 0000000..da3bb17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmin-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c
new file mode 100644 (file)
index 0000000..ff1d0bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmin-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h
new file mode 100644 (file)
index 0000000..459f58d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] < b[i] ? a[i] : b[i];              \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vmins_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] < b ? a[i] : b;                    \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c
new file mode 100644 (file)
index 0000000..19e38ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmul-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 2;                            \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 2 * VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 3;                           \
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 3 * VAL);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c
new file mode 100644 (file)
index 0000000..f4df04d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmul-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c
new file mode 100644 (file)
index 0000000..a21bae4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vmul-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h
new file mode 100644 (file)
index 0000000..b029c06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] * b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] * b;                               \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c
new file mode 100644 (file)
index 0000000..e5eb1c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c
@@ -0,0 +1,69 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vor-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 123;                          \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);  \
+  for (int i = 0; i < SZ; i++)         \
+    assert (a##TYPE[i] == (123 | VAL));
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 123;                         \
+  vors_##TYPE (as##TYPE, as##TYPE, VAL, SZ);   \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == (123 | VAL));
+
+#define RUN3(TYPE,VAL)                         \
+  TYPE ai##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    ai##TYPE[i] = VAL;                         \
+  vori_##TYPE (ai##TYPE, ai##TYPE, SZ);                \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (ai##TYPE[i] == (VAL | 15));
+
+#define RUN3M(TYPE,VAL)                                \
+  TYPE aim##TYPE[SZ];                          \
+  for (int i = 0; i < SZ; i++)                 \
+    aim##TYPE[i] = VAL;                                \
+  vorim_##TYPE (aim##TYPE, aim##TYPE, SZ);     \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (aim##TYPE[i] == (VAL | -16));
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)    \
+ RUN3M(int16_t, 13)    \
+ RUN3(uint16_t, 14)    \
+ RUN3M(int32_t, 15)    \
+ RUN3(uint32_t, 16)    \
+ RUN3M(int64_t, 17)    \
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c
new file mode 100644 (file)
index 0000000..fc76d1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vor-template.h"
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c
new file mode 100644 (file)
index 0000000..d364871
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vor-template.h"
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h
new file mode 100644 (file)
index 0000000..859ae67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] | b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n) \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] | b;                               \
+  }
+
+#define TEST3_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vori_##TYPE (TYPE *dst, TYPE *a, int n)         \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] | 15;                              \
+  }
+
+#define TEST3M_TYPE(TYPE)                              \
+  __attribute__((noipa))                               \
+  void vorim_##TYPE (TYPE *dst, TYPE *a, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] | -16;                             \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)  \
+ TEST3_TYPE(uint16_t)  \
+ TEST3M_TYPE(int32_t)  \
+ TEST3_TYPE(uint32_t)  \
+ TEST3M_TYPE(int64_t)  \
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c
new file mode 100644 (file)
index 0000000..db3bee3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vrem-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 37;                           \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vrem_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 37 % VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 89;                          \
+  vrems_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 89 % VAL);
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c
new file mode 100644 (file)
index 0000000..28cba51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vrem-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vrem.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c
new file mode 100644 (file)
index 0000000..68dbdcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vrem-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vrem.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h
new file mode 100644 (file)
index 0000000..71eebc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vrem_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] % b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vrems_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] % b;                               \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c
new file mode 100644 (file)
index 0000000..8c6d8e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vsub-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 999;                          \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == 999 - VAL);
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 999;                         \
+  vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == 999 - VAL);
+
+#define RUN_ALL()      \
+ RUN(int16_t, 1)       \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, 3)       \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, 5)       \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, 7)      \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, 9)      \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, 11)     \
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c
new file mode 100644 (file)
index 0000000..e2bdd0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vsub-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c
new file mode 100644 (file)
index 0000000..26867a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vsub-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h
new file mode 100644 (file)
index 0000000..0566f3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vsub_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] - b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vsubs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] - b;                               \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c
new file mode 100644 (file)
index 0000000..68b9648
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c
@@ -0,0 +1,69 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vxor-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)                          \
+  TYPE a##TYPE[SZ];                            \
+  TYPE b##TYPE[SZ];                            \
+  for (int i = 0; i < SZ; i++)                 \
+  {                                            \
+    a##TYPE[i] = 123;                          \
+    b##TYPE[i] = VAL;                          \
+  }                                            \
+  vxor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (a##TYPE[i] == (123 ^ VAL));
+
+#define RUN2(TYPE,VAL)                         \
+  TYPE as##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    as##TYPE[i] = 123;                         \
+  vxors_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (as##TYPE[i] == (123 ^ VAL));
+
+#define RUN3(TYPE,VAL)                         \
+  TYPE ai##TYPE[SZ];                           \
+  for (int i = 0; i < SZ; i++)                 \
+    ai##TYPE[i] = VAL;                         \
+  vxori_##TYPE (ai##TYPE, ai##TYPE, SZ);       \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (ai##TYPE[i] == (VAL ^ 15));
+
+#define RUN3M(TYPE,VAL)                                \
+  TYPE aim##TYPE[SZ];                          \
+  for (int i = 0; i < SZ; i++)                 \
+    aim##TYPE[i] = VAL;                                \
+  vxorim_##TYPE (aim##TYPE, aim##TYPE, SZ);    \
+  for (int i = 0; i < SZ; i++)                 \
+    assert (aim##TYPE[i] == (VAL ^ -16));
+
+#define RUN_ALL()      \
+ RUN(int16_t, -1)      \
+ RUN(uint16_t, 2)      \
+ RUN(int32_t, -3)      \
+ RUN(uint32_t, 4)      \
+ RUN(int64_t, -5)      \
+ RUN(uint64_t, 6)      \
+ RUN2(int16_t, -7)     \
+ RUN2(uint16_t, 8)     \
+ RUN2(int32_t, -9)     \
+ RUN2(uint32_t, 10)    \
+ RUN2(int64_t, -11)    \
+ RUN2(uint64_t, 12)    \
+ RUN3M(int16_t, 13)    \
+ RUN3(uint16_t, 14)    \
+ RUN3M(int32_t, 15)    \
+ RUN3(uint32_t, 16)    \
+ RUN3M(int64_t, 17)    \
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c
new file mode 100644 (file)
index 0000000..fbef4a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vxor-template.h"
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c
new file mode 100644 (file)
index 0000000..3e5885e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "vxor-template.h"
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h
new file mode 100644 (file)
index 0000000..954a247
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE)                                \
+  __attribute__((noipa))                               \
+  void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] ^ b[i];                            \
+  }
+
+#define TEST2_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vxors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] ^ b;                               \
+  }
+
+#define TEST3_TYPE(TYPE)                               \
+  __attribute__((noipa))                               \
+  void vxori_##TYPE (TYPE *dst, TYPE *a, int n)                \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] ^ 15;                              \
+  }
+
+#define TEST3M_TYPE(TYPE)                              \
+  __attribute__((noipa))                               \
+  void vxorim_##TYPE (TYPE *dst, TYPE *a, int n)       \
+  {                                                    \
+    for (int i = 0; i < n; i++)                                \
+      dst[i] = a[i] ^ -16;                             \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()     \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)   \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)   \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)   \
+ TEST2_TYPE(uint16_t)  \
+ TEST2_TYPE(int32_t)   \
+ TEST2_TYPE(uint32_t)  \
+ TEST2_TYPE(int64_t)   \
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)  \
+ TEST3_TYPE(uint16_t)  \
+ TEST3M_TYPE(int32_t)  \
+ TEST3_TYPE(uint32_t)  \
+ TEST3M_TYPE(int64_t)  \
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()