perf/x86/intel/cstate: Add Wildcat Lake support

Wildcat Lake (WCL) is a low-power variant of Panther Lake.  From a
C-state profiling perspective, it supports the same residency counters:
CC1/CC6/CC7 and PC2/PC6/PC10.

Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251215182520.115822-1-zide.chen@intel.com

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index fa67fda6e45b4ab8c11b560e60a233a6a353ccd9..b719b0a68a2a1a2b2922b270b1295f4521160762 100644 (file)
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
  *     MSR_CORE_C1_RES: CORE C1 Residency Counter
  *                      perf code: 0x00
  *                      Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- *                                       MTL,SRF,GRR,ARL,LNL,PTL
+ *                                       MTL,SRF,GRR,ARL,LNL,PTL,WCL
  *                      Scope: Core (each processor core has a MSR)
  *     MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *                            perf code: 0x01
@@ -53,19 +53,19 @@
  *                            Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *                                             SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *                                             GRR,ARL,LNL,PTL
+ *                                             GRR,ARL,LNL,PTL,WCL
  *                            Scope: Core
  *     MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *                            perf code: 0x03
  *                            Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
  *                                             ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
- *                                             PTL
+ *                                             PTL,WCL
  *                            Scope: Core
  *     MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
  *                            perf code: 0x00
  *                            Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
  *                                             KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- *                                             RPL,SPR,MTL,ARL,LNL,SRF,PTL
+ *                                             RPL,SPR,MTL,ARL,LNL,SRF,PTL,WCL
  *                            Scope: Package (physical package)
  *     MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
  *                            perf code: 0x01
@@ -78,7 +78,7 @@
  *                            Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *                                             SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
  *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- *                                             ARL,LNL,PTL
+ *                                             ARL,LNL,PTL,WCL
  *                            Scope: Package (physical package)
  *     MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
  *                            perf code: 0x03
@@ -97,7 +97,8 @@
  *     MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
  *                            perf code: 0x06
  *                            Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
- *                                             TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
+ *                                             TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL,
+ *                                             WCL
  *                            Scope: Package (physical package)
  *     MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
  *                            perf code: 0x00
@@ -654,6 +655,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
        X86_MATCH_VFM(INTEL_ARROWLAKE_U,        &adl_cstates),
        X86_MATCH_VFM(INTEL_LUNARLAKE_M,        &lnl_cstates),
        X86_MATCH_VFM(INTEL_PANTHERLAKE_L,      &lnl_cstates),
+       X86_MATCH_VFM(INTEL_WILDCATLAKE_L,      &lnl_cstates),
        { },
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);