clk: sunxi-ng: d1: Add missing divider for MMC mod clocks

[ Upstream commit 98e6da673cc6dd46ca9a599802bd2c8f83606710 ]

The D1/R528/T113 SoCs have a hidden divider of 2 in the MMC mod clocks,
just as other recent SoCs. So far we did not describe that, which led
to the resulting MMC clock rate to be only half of its intended value.

Use a macro that allows to describe a fixed post-divider, to compensate
for that divisor.

This brings the MMC performance on those SoCs to its expected level,
so about 23 MB/s for SD cards, instead of the 11 MB/s measured so far.

Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250501120631.837186-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
index bb66c906ebbb62fe8af1fbae3ebe1a324dfa9a4e..e83d4fd40240fa651b7b42326532ab8699ed0a30 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c
@@ -412,19 +412,23 @@ static const struct clk_parent_data mmc0_mmc1_parents[] = {
        { .hw = &pll_periph0_2x_clk.common.hw },
        { .hw = &pll_audio1_div2_clk.common.hw },
 };
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
-                                      0, 4,    /* M */
-                                      8, 2,    /* P */
-                                      24, 3,   /* mux */
-                                      BIT(31), /* gate */
-                                      0);
-
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
-                                      0, 4,    /* M */
-                                      8, 2,    /* P */
-                                      24, 3,   /* mux */
-                                      BIT(31), /* gate */
-                                      0);
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
+                                              mmc0_mmc1_parents, 0x830,
+                                              0, 4,            /* M */
+                                              8, 2,            /* P */
+                                              24, 3,           /* mux */
+                                              BIT(31),         /* gate */
+                                              2,               /* post-div */
+                                              0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
+                                              mmc0_mmc1_parents, 0x834,
+                                              0, 4,            /* M */
+                                              8, 2,            /* P */
+                                              24, 3,           /* mux */
+                                              BIT(31),         /* gate */
+                                              2,               /* post-div */
+                                              0);
 
 static const struct clk_parent_data mmc2_parents[] = {
        { .fw_name = "hosc" },
@@ -433,12 +437,14 @@ static const struct clk_parent_data mmc2_parents[] = {
        { .hw = &pll_periph0_800M_clk.common.hw },
        { .hw = &pll_audio1_div2_clk.common.hw },
 };
-static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
-                                      0, 4,    /* M */
-                                      8, 2,    /* P */
-                                      24, 3,   /* mux */
-                                      BIT(31), /* gate */
-                                      0);
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc2_parents,
+                                              0x838,
+                                              0, 4,            /* M */
+                                              8, 2,            /* P */
+                                              24, 3,           /* mux */
+                                              BIT(31),         /* gate */
+                                              2,               /* post-div */
+                                              0);
 
 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
                          0x84c, BIT(0), 0);

diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h
index 6e50f3728fb5f1ed31329d3fb961c2442a71ea37..7d836a9fb3db34b201559e2a00d4a2a846fdaf39 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_mp.h
+++ b/drivers/clk/sunxi-ng/ccu_mp.h
@@ -52,6 +52,28 @@ struct ccu_mp {
                }                                                       \
        }
 
+#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, \
+                                               _reg,                   \
+                                               _mshift, _mwidth,       \
+                                               _pshift, _pwidth,       \
+                                               _muxshift, _muxwidth,   \
+                                               _gate, _postdiv, _flags)\
+       struct ccu_mp _struct = {                                       \
+               .enable = _gate,                                        \
+               .m      = _SUNXI_CCU_DIV(_mshift, _mwidth),             \
+               .p      = _SUNXI_CCU_DIV(_pshift, _pwidth),             \
+               .mux    = _SUNXI_CCU_MUX(_muxshift, _muxwidth),         \
+               .fixed_post_div = _postdiv,                             \
+               .common = {                                             \
+                       .reg            = _reg,                         \
+                       .features       = CCU_FEATURE_FIXED_POSTDIV,    \
+                       .hw.init        = CLK_HW_INIT_PARENTS_DATA(_name, \
+                                                       _parents,       \
+                                                       &ccu_mp_ops,    \
+                                                       _flags),        \
+               }                                                       \
+       }
+
 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg,     \
                                   _mshift, _mwidth,                    \
                                   _pshift, _pwidth,                    \