drm/amd/pm: Add message control for SMUv11

Initialize smu message control in SMUv11 SOCs.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index d18934c6fbd5062322b681df889be7fd9ac042cc..97c19005952c1e89f4689c832bd0359ed6e4fde6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -283,6 +283,8 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
 int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
 
 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
+void smu_v11_0_init_msg_ctl(struct smu_context *smu,
+                           const struct cmn2asic_msg_mapping *message_map);
 
 #endif
 #endif

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 81241976b53c62d2e0ff8b76e9bbbeded81e1cf2..eadd81e413aa8963f3438ac23dbafb3d93217107 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1966,4 +1966,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
        smu->pwr_src_map = arcturus_pwr_src_map;
        smu->workload_map = arcturus_workload_map;
        smu_v11_0_set_smu_mailbox_registers(smu);
+       smu_v11_0_init_msg_ctl(smu, arcturus_message_map);
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 51f0e299b840c820d789843c732cf5272be162ad..5ae6ee87de0443783efce189e3b4ea3ef1c5a59d 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -605,4 +605,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
        smu->table_map = cyan_skillfish_table_map;
        smu->is_apu = true;
        smu_v11_0_set_smu_mailbox_registers(smu);
+       smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map);
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 74f24618485a42eec91e6f141a1b88e5989f6acc..3596cb7f8adf21e2a4377e71dab56997213b89f4 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3376,4 +3376,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
        smu->pwr_src_map = navi10_pwr_src_map;
        smu->workload_map = navi10_workload_map;
        smu_v11_0_set_smu_mailbox_registers(smu);
+       smu_v11_0_init_msg_ctl(smu, navi10_message_map);
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3f3947dc52a904eb82675c5e63f09752fa6c229d..9ea6b0d1954b84cafc8e690ea41c16ebe3724d7a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3189,4 +3189,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
        smu->pwr_src_map = sienna_cichlid_pwr_src_map;
        smu->workload_map = sienna_cichlid_workload_map;
        smu_v11_0_set_smu_mailbox_registers(smu);
+       smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map);
 }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 3d03010abcc1b1569b6f28e6c2e76e2a1651df08..579b1dbd36acd0d67ddd4c8d3d4fed6bfdaa3d90 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2176,3 +2176,20 @@ void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
        smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
        smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
+
+void smu_v11_0_init_msg_ctl(struct smu_context *smu,
+                           const struct cmn2asic_msg_mapping *message_map)
+{
+       struct amdgpu_device *adev = smu->adev;
+       struct smu_msg_ctl *ctl = &smu->msg_ctl;
+
+       ctl->smu = smu;
+       mutex_init(&ctl->lock);
+       ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+       ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+       ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+       ctl->config.num_arg_regs = 1;
+       ctl->ops = &smu_msg_v1_ops;
+       ctl->default_timeout = adev->usec_timeout * 20;
+       ctl->message_map = message_map;
+}

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 65a0302ce875628aff11c6df81c1516ddcceb18b..a645094b029b3ae943e52d2be3b43297f0ccedf7 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -2569,4 +2569,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
        smu->workload_map = vangogh_workload_map;
        smu->is_apu = true;
        smu_v11_0_set_smu_mailbox_registers(smu);
+       smu_v11_0_init_msg_ctl(smu, vangogh_message_map);
 }