nvptx: Tweak constraints on copysign instructions

Many thanks to Thomas Schwinge for confirming my hypothesis that the register
usage regression, PR target/104345, is solely due to libgcc's _muldc3 function.
In addition to the isinf functionality in the previously proposed nvptx patch at
https://gcc.gnu.org/pipermail/gcc-patches/2022-January/588453.html which
significantly reduces the number of instructions in _muldc3, the patch below
further reduces both the number of instructions and the number of explicitly
declared registers, by permitting floating point constant immediate operands
in nvptx's copysign instruction.

Fingers-crossed, the combination with all of the previous proposed nvptx
patches improves things.  Ultimately, increasing register usage from 50 to
51 registers, reducing the number of concurrent threads by ~2%, can easily
be countered if we're now executing significantly fewer instructions in each
kernel, for a net performance win.

This patch has been tested on nvptx-none hosted on x86_64-pc-linux-gnu
with a "make" and "make -k check" with no new failures.

gcc/ChangeLog:

	* config/nvptx/nvptx.md (copysign<mode>3): Allow immediate
	floating point constants as operands 1 and/or 2.

diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index ad642e78ae333c9a237104f1c99276ccc7378c90..bb0c0b3b9a5e491f4c250026d08ac101bb101559 100644 (file)
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -1209,8 +1209,8 @@
 
 (define_insn "copysign<mode>3"
   [(set (match_operand:SDFM 0 "nvptx_register_operand" "=R")
-       (unspec:SDFM [(match_operand:SDFM 1 "nvptx_register_operand" "R")
-                     (match_operand:SDFM 2 "nvptx_register_operand" "R")]
+       (unspec:SDFM [(match_operand:SDFM 1 "nvptx_nonmemory_operand" "RF")
+                     (match_operand:SDFM 2 "nvptx_nonmemory_operand" "RF")]
                      UNSPEC_COPYSIGN))]
   ""
   "%.\\tcopysign%t0\\t%0, %2, %1;")