]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/radeon/dce6: add missing display reg for tiling setup
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 5 Apr 2013 14:28:08 +0000 (10:28 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 11 May 2013 20:54:04 +0000 (13:54 -0700)
commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.

A new tiling config register for the display blocks was
added on DCE6.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=62889
https://bugs.freedesktop.org/show_bug.cgi?id=57919

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h
drivers/gpu/drm/radeon/si.c
drivers/gpu/drm/radeon/sid.h

index b64e55dac7571672a6a734dddc1f591646abfde1..ccc3987080bd0ba92ba530eaac9505bfab6f9dd0 100644 (file)
@@ -619,6 +619,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       if (ASIC_IS_DCE6(rdev))
+               WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
index 48e5022ee921d33081f86de17d8ab6b0520ea037..e045f8cbcd4f4ac1ebf24149cfff274614acaa95 100644 (file)
 #define ARUBA_GB_ADDR_CONFIG_GOLDEN        0x12010001
 
 #define DMIF_ADDR_CONFIG                               0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_GFX_CNTL                                   0x0E44
 #define                RINGID(x)                                       (((x) & 0x3) << 0)
 #define                VMID(x)                                         (((x) & 0x7) << 0)
index dd007214dfffdd8edc178e25e2445e5fcc18c3e2..47550ecfba24cacbfa716878ea89698268e15d85 100644 (file)
@@ -1659,6 +1659,7 @@ static void si_gpu_init(struct radeon_device *rdev)
 
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
index c056aae814f090693a4eb445d83d3ca2be30efd7..e9a01f025dcd2545659ce157d39911bb81329073 100644 (file)
@@ -60,6 +60,8 @@
 
 #define DMIF_ADDR_CONFIG                               0xBD4
 
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_STATUS                                     0xE50
 
 #define        SRBM_SOFT_RESET                                 0x0E60