[AArch64] Fix early-clobber operands to vtbx[1,3]

gcc/
	* config/aarch64/arm_neon.h
	(vtbx<1,3>_<psu>8): Fix register constriants.

From-SVN: r203478

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9f4e2975ae0105900de2615bb877e137ef2c0eb1..b0fd76c3782c92d00693c7c8105f7ac0916b85e1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-10-12  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/aarch64/arm_neon.h
+       (vtbx<1,3>_<psu>8): Fix register constriants.
+
 2013-10-11  Jeff Law  <law@redhat.com>
 
        PR tree-optimization/58640

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 482d7d03ed4995d46bef14a0c2c42903aafc6986..f7c9db692a48575a3772214d08ae35f491ad8a73 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -15636,7 +15636,7 @@ vtbx1_s8 (int8x8_t r, int8x8_t tab, int8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {%2.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "w"(temp), "w"(idx), "w"(r)
            : /* No clobbers */);
   return result;
@@ -15652,7 +15652,7 @@ vtbx1_u8 (uint8x8_t r, uint8x8_t tab, uint8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {%2.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "w"(temp), "w"(idx), "w"(r)
            : /* No clobbers */);
   return result;
@@ -15668,7 +15668,7 @@ vtbx1_p8 (poly8x8_t r, poly8x8_t tab, uint8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {%2.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "w"(temp), "w"(idx), "w"(r)
            : /* No clobbers */);
   return result;
@@ -15723,7 +15723,7 @@ vtbx3_s8 (int8x8_t r, int8x8x3_t tab, int8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "Q"(temp), "w"(idx), "w"(r)
            : "v16", "v17", "memory");
   return result;
@@ -15742,7 +15742,7 @@ vtbx3_u8 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "Q"(temp), "w"(idx), "w"(r)
            : "v16", "v17", "memory");
   return result;
@@ -15761,7 +15761,7 @@ vtbx3_p8 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx)
           "cmhs %0.8b, %3.8b, %0.8b\n\t"
           "tbl %1.8b, {v16.16b - v17.16b}, %3.8b\n\t"
           "bsl %0.8b, %4.8b, %1.8b\n\t"
-           : "+w"(result), "=w"(tmp1)
+           : "+w"(result), "=&w"(tmp1)
            : "Q"(temp), "w"(idx), "w"(r)
            : "v16", "v17", "memory");
   return result;