RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a (possibly negated) minus-mult RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f        v6,fa0
  vfnmacc.vv      v2,v6,v4

After, we get only one:
  vfnmacc.vf      v2,fa0,v4

	PR target/119100

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vfnmsub_<mode>,*vfnmadd_<mode>): Handle
	both add and acc variants.
	* config/riscv/vector.md (*pred_mul_neg_<optab><mode>_scalar_undef): New
	pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfnmacc and
	vfnmsac.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h (DEF_VF_MULOP_CASE_1):
	Fix return type.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c: New test.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index bb15d14b4e64396dd9b11997767e8bd69aabd8ba..8df7f6494cf78e313c14c8c352d61fb996d62937 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1723,6 +1723,8 @@
 ;; - vfnmsub.vf
 ;; - vfmacc.vf
 ;; - vfmsac.vf
+;; - vfnmacc.vf
+;; - vfnmsac.vf
 ;; =============================================================================
 
 ;; vfmadd.vf, vfmsub.vf, vfmacc.vf, vfmsac.vf
@@ -1748,22 +1750,22 @@
   [(set_attr "type" "vfmuladd")]
 )
 
-;; vfnmsub.vf
+;; vfnmsub.vf, vfnmsac.vf
 (define_insn_and_split "*vfnmsub_<mode>"
-  [(set (match_operand:V_VLSF 0 "register_operand"             "=vd")
+  [(set (match_operand:V_VLSF 0 "register_operand")
     (minus:V_VLSF
-           (match_operand:V_VLSF 3 "register_operand"          " vr")
-           (mult:V_VLSF
-             (vec_duplicate:V_VLSF
-               (match_operand:<VEL> 1 "register_operand"       "  f"))
-             (match_operand:V_VLSF 2 "register_operand"        "  0"))))]
+      (match_operand:V_VLSF 3 "register_operand")
+      (mult:V_VLSF
+       (vec_duplicate:V_VLSF
+         (match_operand:<VEL> 1 "register_operand"))
+       (match_operand:V_VLSF 2 "register_operand"))))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
   {
     rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
-                operands[2]};
+                RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg_scalar (PLUS, <MODE>mode),
                                   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1771,23 +1773,23 @@
   [(set_attr "type" "vfmuladd")]
 )
 
-;; vfnmadd.vf
+;; vfnmadd.vf, vfnmacc.vf
 (define_insn_and_split "*vfnmadd_<mode>"
-  [(set (match_operand:V_VLSF 0 "register_operand"     "=vd")
+  [(set (match_operand:V_VLSF 0 "register_operand")
     (minus:V_VLSF
       (mult:V_VLSF
        (neg:V_VLSF
-         (match_operand:V_VLSF 2 "register_operand"    "  0"))
+         (match_operand:V_VLSF 2 "register_operand"))
        (vec_duplicate:V_VLSF
-         (match_operand:<VEL> 1 "register_operand"     "  f")))
-      (match_operand:V_VLSF 3 "register_operand"       " vr")))]
+         (match_operand:<VEL> 1 "register_operand")))
+      (match_operand:V_VLSF 3 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
   {
     rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
-                operands[2]};
+                RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg_scalar (MINUS, <MODE>mode),
                                   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index aaea115339381197ac28a2a235efb8664e90b4bd..6753b01db599b6feba9ea518b0b2a3f9625ea4a2 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6848,9 +6848,43 @@
                  (match_operand:<VEL> 2 "register_operand"))
                (match_operand:V_VLSF 3 "register_operand")))
            (match_operand:V_VLSF 4 "register_operand"))
-         (match_operand:V_VLSF 5 "register_operand")))]
+         (match_operand:V_VLSF 5 "vector_merge_operand")))]
   "TARGET_VECTOR"
-{})
+{
+  riscv_vector::prepare_ternary_operands (operands);
+})
+
+(define_insn "*pred_mul_neg_<optab><mode>_scalar_undef"
+  [(set (match_operand:V_VLSF 0 "register_operand"           "=vd,vd, vr, vr")
+       (if_then_else:V_VLSF
+         (unspec:<VM>
+           [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+            (match_operand 6 "vector_length_operand"    "rvl,rvl,rvl,rvl")
+            (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 9 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 10 "const_int_operand"       "  i,  i,  i,  i")
+            (reg:SI VL_REGNUM)
+            (reg:SI VTYPE_REGNUM)
+            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+         (plus_minus:V_VLSF
+           (neg:V_VLSF
+             (mult:V_VLSF
+               (vec_duplicate:V_VLSF
+                 (match_operand:<VEL> 3 "register_operand"  "  f,  f,  f,  f"))
+               (match_operand:V_VLSF 4 "register_operand"   "  0, vr,  0, vr")))
+           (match_operand:V_VLSF 5 "register_operand"       " vr,  0, vr,  0"))
+         (match_operand:V_VLSF 2 "vector_undef_operand")))]
+  "TARGET_VECTOR"
+  "@
+   vf<nmsub_nmadd>.vf\t%0,%3,%5%p1
+   vf<nmsac_nmacc>.vf\t%0,%3,%4%p1
+   vf<nmsub_nmadd>.vf\t%0,%3,%5%p1
+   vf<nmsac_nmacc>.vf\t%0,%3,%4%p1"
+  [(set_attr "type" "vfmuladd")
+   (set_attr "mode" "<MODE>")
+   (set (attr "frm_mode")
+       (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
 
 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
   [(set (match_operand:V_VLSF 0 "register_operand"            "=vd, vr")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 10ee2d82597ffa0a75764e4fc56cb5f8b3a78017..05cf57cc8cbdf46cbc06ded41d23b9765508db9d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_0 (_Float16, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (_Float16, -, -, nsub)
 DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc)
 DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac)
+DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc)
+DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac)
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index 3492c7f1ff8246e45876eb7606a1ff883765ff26..873e315134705d16b4780234b401f5697a5083c8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_0 (float, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (float, -, -, nsub)
 DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc)
 DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac)
+DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc)
+DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac)
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 3ee2fbb9cd5d277dc39a41fca708d0b2f2d251b5..4de038c62994471998e78c490895a05c687e4d9c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_0 (double, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (double, -, -, nsub)
 DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc)
 DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
+DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
+DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 1e4b8064228b67adf44b520eea88035abff89f6b..78127b6dabbfe8bab42c3241766c347fc7b508bd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 48d87c4a690bd4b70fbce14e57d4d6c60bab495d..30d57e0c75719c2c67c32f193d5aff54679ecaeb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index ad7beab26241b97e674e49097af738f461ec64dc..a2ac67e4a8d9592993a8a9fd112d6eec6f002b77 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 47f7cd1790c8fa57683ed27a8e73c67b68d0dd4e..8295ffb7d5300a6f51b42469c6b6b4050c971819 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128)
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler {vfmacc.vf} } } */
 /* { dg-final { scan-assembler {vfmsac.vf} } } */
+/* { dg-final { scan-assembler {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 5877dec8b189c131e1a0a69e682739b97a56c778..f237f848d03b2102096c24419b5ad6b49fe7a963 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128)
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler {vfmacc.vf} } } */
 /* { dg-final { scan-assembler {vfmsac.vf} } } */
+/* { dg-final { scan-assembler {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 7073502e00ee5bd58bf4a92ec57b076c7e570181..71bd7e1b9573e065727351efb749a5cdb44795ad 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -9,6 +9,8 @@ DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -16,3 +18,5 @@ DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler {vfmacc.vf} } } */
 /* { dg-final { scan-assembler {vfmsac.vf} } } */
+/* { dg-final { scan-assembler {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index dc7f252ce37f34939cc2f1d0f8bd5ad816025fd2..7a50f674337e97ac426178474ef6da9fd095b281 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index c62711fb40fb2baa6a5800aa960fa3cd429eb44f..fb0493ea72c9914315ec4f2b174d6bda07ffe757 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index d0c82cf41f2121779d68aee7a4f61ef8a76a765c..d71bdde26afe2b4b6b126b8bf248ad894e3044ff 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -9,3 +9,5 @@
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmacc.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsac.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
index 98fa8fa42df2153e540f136fc6a0e2d38a4eccd9..1659f78beea3be6e0b56c93ae34c808a55f4182b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
@@ -113,8 +113,9 @@
   VF_MULOP_ACC_BODY_X128 (op, neg)
 
 #define DEF_VF_MULOP_ACC_CASE_1(T, OP, NEG, NAME, BODY)                        \
-  T test_vf_mulop_acc_##NAME##_##T##_case_1 (T *restrict out, T *restrict in,  \
-                                            T x, unsigned n)                  \
+  void test_vf_mulop_acc_##NAME##_##T##_case_1 (T *restrict out,               \
+                                               T *restrict in, T x,           \
+                                               unsigned n)                    \
   {                                                                            \
     unsigned k = 0;                                                            \
     T tmp = x + 3;                                                             \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
new file mode 100644 (file)
index 0000000..b960e7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    _Float16
+#define NAME nadd
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c
new file mode 100644 (file)
index 0000000..b97cdc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    float
+#define NAME nadd
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c
new file mode 100644 (file)
index 0000000..8da279f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    double
+#define NAME nadd
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
new file mode 100644 (file)
index 0000000..4f10600
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    _Float16
+#define NAME nsub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c
new file mode 100644 (file)
index 0000000..be1084a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    float
+#define NAME nsub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c
new file mode 100644 (file)
index 0000000..73b5a6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    double
+#define NAME nsub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"