* removes --vex-guest-chase-cond=no|yes. This was never used in practice.
* rename --vex-guest-chase-thresh=<0..99> to --vex-guest-chase=no|yes. In
otherwords, downgrade it from a numeric flag to a boolean one, that can
simply disable all chasing if required. (Some tools, notably Callgrind,
force-disable block chasing, so this functionality at least needs to be
retained).
vassert(sizeof(HWord) == sizeof(void*));
vassert(vex_control.guest_max_insns >= 1);
vassert(vex_control.guest_max_insns <= 100);
- vassert(vex_control.guest_chase_thresh >= 0);
- vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
+ vassert(vex_control.guest_chase == False || vex_control.guest_chase == True);
vassert(guest_word_type == Ity_I32 || guest_word_type == Ity_I64);
if (guest_word_type == Ity_I32) {
// Reasons to give up immediately:
// User or tool asked us not to chase
- if (vex_control.guest_chase_thresh == 0)
+ if (!vex_control.guest_chase)
break;
// Out of extent slots
BBs longer than this are split up. Default=60 (guest
insns). */
Int guest_max_insns;
- /* How aggressive should front ends be in following
- unconditional branches to known destinations? Default=10,
- meaning that if a block contains less than 10 guest insns so
- far, the front end(s) will attempt to chase into its
- successor. A setting of zero disables chasing. */
- // FIXME change this to a Bool
- Int guest_chase_thresh;
- /* EXPERIMENTAL: chase across conditional branches? Not all
- front ends honour this. Default: NO. */
- // FIXME remove this completely.
- Bool guest_chase_cond;
+ /* Should Vex try to construct superblocks, by chasing unconditional
+ branches/calls to known destinations, and performing AND/OR idiom
+ recognition? It is recommended to set this to True as that possibly
+ improves performance a bit, and also is important for avoiding certain
+ kinds of false positives in Memcheck. Default=True. */
+ Bool guest_chase;
/* Register allocator version. Allowed values are:
- '2': previous, good and slow implementation.
- '3': current, faster implementation; perhaps producing slightly worse
"=> resetting it back to 0\n");
VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overridden.
}
- if (VG_(clo_vex_control).guest_chase_thresh != 0) {
+ if (VG_(clo_vex_control).guest_chase) {
VG_(message)(Vg_UserMsg,
- "callgrind only works with --vex-guest-chase-thresh=0\n"
- "=> resetting it back to 0\n");
- VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overridden.
+ "callgrind only works with --vex-guest-chase=no\n"
+ "=> resetting it back to 'no'\n");
+ VG_(clo_vex_control).guest_chase = False; // cannot be overridden.
}
CLG_DEBUG(1, " dump threads: %s\n", CLG_(clo).separate_threads ? "Yes":"No");
= VexRegUpdSpAtMemAccess; // overridable by the user.
VG_(clo_vex_control).iropt_unroll_thresh = 0; // cannot be overridden.
- VG_(clo_vex_control).guest_chase_thresh = 0; // cannot be overridden.
+ VG_(clo_vex_control).guest_chase = False; // cannot be overridden.
VG_(basic_tool_funcs) (CLG_(post_clo_init),
CLG_(instrument),
" --vex-iropt-level=<0..2> [2]\n"
" --vex-iropt-unroll-thresh=<0..400> [120]\n"
" --vex-guest-max-insns=<1..100> [50]\n"
-" --vex-guest-chase-thresh=<0..99> [10]\n"
-" --vex-guest-chase-cond=no|yes [no]\n"
+" --vex-guest-chase=no|yes [yes]\n"
" Precise exception control. Possible values for 'mode' are as follows\n"
" and specify the minimum set of registers guaranteed to be correct\n"
" immediately prior to memory access instructions:\n"
VG_(clo_vex_control).iropt_unroll_thresh, 0, 400) {}
else if VG_BINT_CLO(arg, "--vex-guest-max-insns",
VG_(clo_vex_control).guest_max_insns, 1, 100) {}
- else if VG_BINT_CLO(arg, "--vex-guest-chase-thresh",
- VG_(clo_vex_control).guest_chase_thresh, 0, 99) {}
- else if VG_BOOL_CLO(arg, "--vex-guest-chase-cond",
- VG_(clo_vex_control).guest_chase_cond) {}
+ else if VG_BOOL_CLO(arg, "--vex-guest-chase",
+ VG_(clo_vex_control).guest_chase) {}
else if VG_INT_CLO(arg, "--log-fd", pos->tmp_log_fd) {
pos->log_to = VgLogTo_Fd;
if (VG_(clo_vgdb_prefix) == NULL)
VG_(clo_vgdb_prefix) = VG_(vgdb_prefix_default)();
- /* Make VEX control parameters sane */
-
- if (VG_(clo_vex_control).guest_chase_thresh
- >= VG_(clo_vex_control).guest_max_insns)
- VG_(clo_vex_control).guest_chase_thresh
- = VG_(clo_vex_control).guest_max_insns - 1;
-
- if (VG_(clo_vex_control).guest_chase_thresh < 0)
- VG_(clo_vex_control).guest_chase_thresh = 0;
-
/* Check various option values */
if (VG_(clo_verbosity) < 0)
(gdb) p vex_control
$5 = {iropt_verbosity = 0, iropt_level = 2,
iropt_register_updates = VexRegUpdUnwindregsAtMemAccess,
- iropt_unroll_thresh = 120, guest_max_insns = 60, guest_chase_thresh = 10,
- guest_chase_cond = 0 '\000'}
+ iropt_unroll_thresh = 120, guest_max_insns = 60, guest_chase_thresh = 10}
(gdb)
]]></screen>
</listitem>
/* Try a closer approximation of basic blocks */
/* This is the same as the command line option */
- /* --vex-guest-chase-thresh=0 */
- VG_(clo_vex_control).guest_chase_thresh = 0;
+ /* --vex-guest-chase=no */
+ VG_(clo_vex_control).guest_chase = False;
}
/* Parse the command line options */
sg_pre_clo_init();
VG_(clo_vex_control).iropt_unroll_thresh = 0;
- VG_(clo_vex_control).guest_chase_thresh = 0;
+ VG_(clo_vex_control).guest_chase = False;
}
VG_DETERMINE_INTERFACE_VERSION(pc_pre_clo_init)
{
Thr* hbthr_root;
- if (HG_(clo_delta_stacktrace)
- && VG_(clo_vex_control).guest_chase_thresh != 0) {
+ if (HG_(clo_delta_stacktrace) && VG_(clo_vex_control).guest_chase) {
if (VG_(clo_verbosity) >= 2)
VG_(message)(Vg_UserMsg,
"helgrind --delta-stacktrace=yes only works with "
- "--vex-guest-chase-thresh=0\n"
- "=> (re-setting it to 0)\n");
- VG_(clo_vex_control).guest_chase_thresh = 0;
+ "--vex-guest-chase=no\n"
+ "=> (re-setting it to 'no')\n");
+ VG_(clo_vex_control).guest_chase = False;
}
--vex-iropt-level=<0..2> [2]
--vex-iropt-unroll-thresh=<0..400> [120]
--vex-guest-max-insns=<1..100> [50]
- --vex-guest-chase-thresh=<0..99> [10]
- --vex-guest-chase-cond=no|yes [no]
+ --vex-guest-chase=no|yes [yes]
Precise exception control. Possible values for 'mode' are as follows
and specify the minimum set of registers guaranteed to be correct
immediately prior to memory access instructions: