clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock

Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (nss) clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250313110359.242491-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 6bb66a7e1fb65d339ecb4c14d9870c660d06545c..6dc86e686de466ffdbff0f605a335cad489ab153 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll0 = {
        },
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+       .offset = 0x20000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .width = 4,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "gpll0_out_aux",
+               .parent_hws = (const struct clk_hw *[]) {
+                       &gpll0_main.clkr.hw
+               },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ro_ops,
+       },
+};
+
 static struct clk_alpha_pll gpll4_main = {
        .offset = 0x22000,
        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
@@ -3896,6 +3910,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
        [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
        [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
        [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
+       [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq9574_resets[] = {