arm64: dts: imx95: add flexcan[1..5] support

Add the flexcan[1..5] nodes for imx95.

Reviewed-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 3f41f728fcd4418ee4e3e2fa862734ba3215fc03..a01ae6e4d0efcead5191c3d210693335a7f237d1 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -713,6 +713,34 @@
                                status = "disabled";
                        };
 
+                       flexcan2: can@425b0000 {
+                               compatible = "fsl,imx95-flexcan";
+                               reg = <0x425b0000 0x10000>;
+                               interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+                                        <&scmi_clk IMX95_CLK_CAN2>;
+                               clock-names = "ipg", "per";
+                               assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;
+                               assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+                               assigned-clock-rates = <40000000>;
+                               fsl,clk-source = /bits/ 8 <0>;
+                               status = "disabled";
+                       };
+
+                       flexcan3: can@42600000 {
+                               compatible = "fsl,imx95-flexcan";
+                               reg = <0x42600000 0x10000>;
+                               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+                                        <&scmi_clk IMX95_CLK_CAN3>;
+                               clock-names = "ipg", "per";
+                               assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;
+                               assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+                               assigned-clock-rates = <40000000>;
+                               fsl,clk-source = /bits/ 8 <0>;
+                               status = "disabled";
+                       };
+
                        flexspi1: spi@425e0000 {
                                compatible = "nxp,imx8mm-fspi";
                                reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
@@ -931,6 +959,34 @@
                                #mbox-cells = <2>;
                                status = "disabled";
                        };
+
+                       flexcan4: can@427c0000 {
+                               compatible = "fsl,imx95-flexcan";
+                               reg = <0x427c0000 0x10000>;
+                               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+                                        <&scmi_clk IMX95_CLK_CAN4>;
+                               clock-names = "ipg", "per";
+                               assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;
+                               assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+                               assigned-clock-rates = <40000000>;
+                               fsl,clk-source = /bits/ 8 <0>;
+                               status = "disabled";
+                       };
+
+                       flexcan5: can@427d0000 {
+                               compatible = "fsl,imx95-flexcan";
+                               reg = <0x427d0000 0x10000>;
+                               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+                                        <&scmi_clk IMX95_CLK_CAN5>;
+                               clock-names = "ipg", "per";
+                               assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;
+                               assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+                               assigned-clock-rates = <40000000>;
+                               fsl,clk-source = /bits/ 8 <0>;
+                               status = "disabled";
+                       };
                };
 
                aips3: bus@42800000 {
@@ -1205,6 +1261,20 @@
                                status = "disabled";
                        };
 
+                       flexcan1: can@443a0000 {
+                               compatible = "fsl,imx95-flexcan";
+                               reg = <0x443a0000 0x10000>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&scmi_clk IMX95_CLK_BUSAON>,
+                                        <&scmi_clk IMX95_CLK_CAN1>;
+                               clock-names = "ipg", "per";
+                               assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;
+                               assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+                               assigned-clock-rates = <40000000>;
+                               fsl,clk-source = /bits/ 8 <0>;
+                               status = "disabled";
+                       };
+
                        sai1: sai@443b0000 {
                                compatible = "fsl,imx95-sai";
                                reg = <0x443b0000 0x10000>;