riscv: dts: microchip: fix mailbox description

When the binding for the mailbox on PolarFire SoC was originally
written, and later modified, mistakes were made - and the precise
nature of the later modification should have been a giveaway, but alas
I was naive at the time.

A more correct modelling of the hardware is to use two syscons and have
a single reg entry for the mailbox, containing the mailbox region. The
two syscons contain the general control/status registers for the mailbox
and the interrupt related registers respectively. The reason for two
syscons is that the same mailbox is present on the non-SoC version of
the FPGA, which has no interrupt controller, and the shared part of the
rtl was unchanged between devices.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 9883ca3554c50a5258aac50ef10a4c98311956ac..f9d6bf08e71703cf1d7b72a257175e0b303fb8ec 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -259,6 +259,11 @@
                        #reset-cells = <1>;
                };
 
+               sysreg_scb: syscon@20003000 {
+                       compatible = "microchip,mpfs-sysreg-scb", "syscon";
+                       reg = <0x0 0x20003000 0x0 0x1000>;
+               };
+
                ccc_se: clock-controller@38010000 {
                        compatible = "microchip,mpfs-ccc";
                        reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
@@ -521,10 +526,14 @@
                        status = "disabled";
                };
 
-               mbox: mailbox@37020000 {
+               control_scb: syscon@37020000 {
+                       compatible = "microchip,mpfs-control-scb", "syscon";
+                       reg = <0x0 0x37020000 0x0 0x100>;
+               };
+
+               mbox: mailbox@37020800 {
                        compatible = "microchip,mpfs-mailbox";
-                       reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
-                             <0x0 0x37020800 0x0 0x100>;
+                       reg = <0x0 0x37020800 0x0 0x1000>;
                        interrupt-parent = <&plic>;
                        interrupts = <96>;
                        #mbox-cells = <1>;