arm64: dts: qcom: ipq: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 7e6e2c1219793145fdbc6d97cac5c1a646dd77b3..8914f2ef0bc47fda243b19174f77ce73fc10757d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -31,27 +31,27 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               CPU1: cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x1>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               L2_0: l2-cache {
+               l2_0: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-size = <0x80000>;

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 71328b22353114f21404450fcf54e2767fa50cd9..d3c3e215a15cfc3998f8e30656828a46b6991898 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -31,47 +31,47 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               CPU1: cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x1>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               CPU2: cpu@2 {
+               cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x2>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               CPU3: cpu@3 {
+               cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x3>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        operating-points-v2 = <&cpu_opp_table>;
                };
 
-               L2_0: l2-cache {
+               l2_0: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 8edd535a188f2ddc8af2f564f514c8be4a8d7a43..dbf6716bcb59a04939c2b994d85cf58c12365962 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -34,12 +34,12 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -47,12 +47,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU1: cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x1>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -60,12 +60,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU2: cpu@2 {
+               cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x2>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -73,12 +73,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU3: cpu@3 {
+               cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x3>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -86,7 +86,7 @@
                        #cooling-cells = <2>;
                };
 
-               L2_0: l2-cache {
+               l2_0: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
@@ -1015,10 +1015,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu_alert>;
-                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 284a4553070faa94960d12e6b08fadf8cd2c6b06..78e1992b749573ea899e4d639eedf437cab19d59 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,39 +32,39 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        enable-method = "psci";
                };
 
-               CPU1: cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x1>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                };
 
-               CPU2: cpu@2 {
+               cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x2>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                };
 
-               CPU3: cpu@3 {
+               cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x3>;
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                };
 
-               L2_0: l2-cache {
+               l2_0: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 14c7b3a78442c85c3b5dab24498aa1740facc22b..d1fd35ebc4a28bafee77e7be441709f99f482558 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -34,12 +34,12 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a73";
                        reg = <0x0>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -47,12 +47,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU1: cpu@1 {
+               cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a73";
                        reg = <0x1>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -60,12 +60,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU2: cpu@2 {
+               cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a73";
                        reg = <0x2>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -73,12 +73,12 @@
                        #cooling-cells = <2>;
                };
 
-               CPU3: cpu@3 {
+               cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a73";
                        reg = <0x3>;
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
                        clock-names = "cpu";
                        operating-points-v2 = <&cpu_opp_table>;
@@ -86,7 +86,7 @@
                        #cooling-cells = <2>;
                };
 
-               L2_0: l2-cache {
+               l2_0: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
@@ -863,10 +863,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu0_alert>;
-                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
@@ -891,10 +891,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu1_alert>;
-                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
@@ -919,10 +919,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu2_alert>;
-                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
@@ -947,10 +947,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu3_alert>;
-                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };