RISC-V: Add SiFive cease extension v1.0

Add SiFive cease extension,
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This aligns LLVM:
* https://llvm.org/docs/RISCVUsage.html
* https://github.com/llvm/llvm-project/pull/83896

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for
	'xsfcease'.
	(riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
	(riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.

gas/ChangeLog:

	* doc/c-riscv.texi: Updated.
	* testsuite/gas/riscv/march-help.l: Updated.
	* testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
	* testsuite/gas/riscv/sifive-insns.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and
	mask encoding for 'sf.cease'.
	* opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for
	'xsfcease'.

opcodes/ChangeLog:

    * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6dc71935c8e2a2a407d94f1db3a9c2691d34fcca..275b2ef848aa5518722567e3b4127a8f3eb0829a 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1485,7 +1485,8 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadvector",     ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xtheadzvamo",      ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
-  {"xsfvcp",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0},
+  {"xsfvcp",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
+  {"xsfcease",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2736,6 +2737,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xventanacondops");
     case INSN_CLASS_XSFVCP:
       return riscv_subset_supports (rps, "xsfvcp");
+    case INSN_CLASS_XSFCEASE:
+      return riscv_subset_supports (rps, "xsfcease");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -3004,6 +3007,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadvector";
     case INSN_CLASS_XTHEADZVAMO:
       return "xtheadzvamo";
+    case INSN_CLASS_XSFCEASE:
+      return "xsfcease";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 61bb7bcdadcc561e7d4db8dddc1e6df026b26a29..e579eeb58c013ede706a333dde32ca9e5f498e54 100644 (file)
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a coprocessor.
 
 It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}.
 
+@item XSfCease
+XSfCease provides an instruction to instigates power-down sequence.
+
+It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
+
 @end table

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index e0d597e15eeb39865b3890a2dc6b2dd12d052259..c33d856686b1e2658dcf52e1be0af5a68d771cce 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -130,3 +130,4 @@ All available -march extensions for RISC-V:
        xtheadzvamo                             1.0
        xventanacondops                         1.0
        xsfvcp                                  1.0
+       xsfcease                                1.0

diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
index f7d63d1bce0486f79b67ffc76fb2dc0400282403..610f62588b3dac17ede62ea82bec383c17e79074 100644 (file)
--- a/gas/testsuite/gas/riscv/sifive-insns.d
+++ b/gas/testsuite/gas/riscv/sifive-insns.d
@@ -35,3 +35,4 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+fc25c05b[     ]+sf.vc.v.xvw[  ]+0x3,v0,v2,a1
 [      ]+[0-9a-f]+:[   ]+fc27b05b[     ]+sf.vc.v.ivw[  ]+0x3,v0,v2,15
 [      ]+[0-9a-f]+:[   ]+fc25d05b[     ]+sf.vc.v.fvw[  ]+0x1,v0,v2,fa1
+[      ]+[0-9a-f]+:[   ]+30500073[     ]+sf.cease

diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
index d593692c5c05f65f0d58e4879f7596ab9c8cc65c..cdf90c1b3ba72e91de7b9c0e30b77a699db6783b 100644 (file)
--- a/gas/testsuite/gas/riscv/sifive-insns.s
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -31,3 +31,9 @@
        sf.vc.v.ivw 0x3, v0, v2, 15
        sf.vc.v.fvw 0x1, v0, v2, fa1
        .option pop
+
+       # xscease
+       .option push
+       .option arch, +xsfcease1p0
+       sf.cease
+       .option pop

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index f87822ab382636474caa0c3e5c4deb0e82d5a9e1..8763cdf3543227ec0e74a8c352ea5de897292d41 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3155,6 +3155,9 @@
 #define MASK_SF_VC_FVW 0xfa00707f
 #define MATCH_SF_VC_V_FVW 0xf800505b
 #define MASK_SF_VC_V_FVW 0xfa00707f
+/* Vendor-specific (SiFive) cease instruction.  */
+#define MATCH_SF_CEASE 0x30500073
+#define MASK_SF_CEASE 0xffffffff
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 20bfdb17fec9b0e6b200a6057f188e8beedf6216..ece2963d531ba36d60803cd29c2885d19287563c 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -515,6 +515,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
   INSN_CLASS_XSFVCP,
+  INSN_CLASS_XSFCEASE,
 };
 
 /* This structure holds information for a particular instruction.  */

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e101c3d1500dcc473df02d46c7e05629dcc82c18..f7c0f5c7c833eda20824e27fb40c3c182a77ed37 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3113,6 +3113,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
 {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
 
+/* Vendor-specific (SiFive) cease instruction.  */
+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };