mailbox: mtk-cmdq: Add GCE hardware virtualization configuration

The GCE hardware virtualization configuration supports the isolation of
GCE hardware resources across different OS environments. Each OS is
treated as a virtual machine (VM) for GCE purposes.
There are 6 VMs and 1 host VM. The host VM has main control over the
GCE virtualization settings for all VMs.

To properly access the GCE thread registers, it is necessary to
configure access permissions for specific GCE threads assigned to
different VMs.
Currently, since only the host VM is being used, it is required to
enable access permissions for all GCE threads for the host VM.

There are 2 VM configurations:
1. VM_ID_MAP
There are 4 registers to allocate 32 GCE threads across different VMs:
VM_ID_MAP0 for threads 0-9, VM_ID_MAP1 for threads 10-19,
VM_ID_MAP2 for threads 20-29, and VM_ID_MAP3 for threads 30-31.
Each thread has a 3-bit configuration, where setting all bits to 1
configures the thread for the host VM.

2. VM_CPR_GSIZE
It is used to allocate the CPR SRAM size to each VM. Each VM has 4-bit
configuration, where setting bit 0-3 to configures the size of host VM.
This setting must be configured before the VM configuration to prevent
resource leakage.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 95e8a5331b7cf37c3bbcd319fe33d1246627135c..a544108ddae769ffebb0a22023f7b1402801fb47 100644 (file)
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -43,6 +43,13 @@
 #define GCE_CTRL_BY_SW                         GENMASK(2, 0)
 #define GCE_DDR_EN                             GENMASK(18, 16)
 
+#define GCE_VM_ID_MAP(n)               (0x5018 + (n) / 10 * 4)
+#define GCE_VM_ID_MAP_THR_FLD_SHIFT(n)         ((n) % 10 * 3)
+#define GCE_VM_ID_MAP_HOST_VM                  GENMASK(2, 0)
+#define GCE_VM_CPR_GSIZE               0x50c4
+#define GCE_VM_CPR_GSIZE_FLD_SHIFT(vm_id)      ((vm_id) * 4)
+#define GCE_VM_CPR_GSIZE_MAX                   GENMASK(3, 0)
+
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES    0x3200
 #define CMDQ_THR_ENABLED               0x1
 #define CMDQ_THR_DISABLED              0x0
@@ -89,6 +96,7 @@ struct gce_plat {
        u8 shift;
        bool control_by_sw;
        bool sw_ddr_en;
+       bool gce_vm;
        u32 gce_num;
 };
 
@@ -120,6 +128,45 @@ u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 }
 EXPORT_SYMBOL(cmdq_get_shift_pa);
 
+static void cmdq_vm_init(struct cmdq *cmdq)
+{
+       int i;
+       u32 vm_cpr_gsize = 0, vm_id_map = 0;
+       u32 *vm_map = NULL;
+
+       if (!cmdq->pdata->gce_vm)
+               return;
+
+       vm_map = kcalloc(cmdq->pdata->thread_nr, sizeof(*vm_map), GFP_KERNEL);
+       if (!vm_map)
+               return;
+
+       /* only configure the max CPR SRAM size to host vm (vm_id = 0) currently */
+       vm_cpr_gsize = GCE_VM_CPR_GSIZE_MAX << GCE_VM_CPR_GSIZE_FLD_SHIFT(0);
+
+       /* set all thread mapping to host vm currently */
+       for (i = 0; i < cmdq->pdata->thread_nr; i++)
+               vm_map[i] = GCE_VM_ID_MAP_HOST_VM << GCE_VM_ID_MAP_THR_FLD_SHIFT(i);
+
+       /* set the amount of CPR SRAM to allocate to each VM */
+       writel(vm_cpr_gsize, cmdq->base + GCE_VM_CPR_GSIZE);
+
+       /* config CPR_GSIZE before setting VM_ID_MAP to avoid data leakage */
+       for (i = 0; i < cmdq->pdata->thread_nr; i++) {
+               vm_id_map |= vm_map[i];
+               /* config every 10 threads, e.g., thread id=0~9, 10~19, ..., into one register */
+               if ((i + 1) % 10 == 0) {
+                       writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(i));
+                       vm_id_map = 0;
+               }
+       }
+       /* config remaining threads settings */
+       if (cmdq->pdata->thread_nr % 10 != 0)
+               writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(cmdq->pdata->thread_nr - 1));
+
+       kfree(vm_map);
+}
+
 static void cmdq_gctl_value_toggle(struct cmdq *cmdq, bool ddr_enable)
 {
        u32 val = cmdq->pdata->control_by_sw ? GCE_CTRL_BY_SW : 0;
@@ -164,6 +211,7 @@ static void cmdq_init(struct cmdq *cmdq)
 
        WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
 
+       cmdq_vm_init(cmdq);
        cmdq_gctl_value_toggle(cmdq, true);
 
        writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);