Daily bump.

diff --git a/ChangeLog b/ChangeLog
index 6c07275d2b4ff45e8fc9069cea71a68e6a441360..9d1ed68299d16470b6085e369f5edb304d2def91 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+2020-10-06  Tobias Burnus  <tobias@codesourcery.com>
+
+       Backported from master:
+       2020-10-06  Tobias Burnus  <tobias@codesourcery.com>
+
+       PR target/97302
+       * configure.ac: Only set with_gmp to /usr/local
+       if not building in tree.
+       * configure: Regenerate.
+
 2020-07-23  Release Manager
 
        * GCC 10.2.0 released.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e4d9a464f36014a57b7bc2908521f1625e35dd4f..55571a745671045117122f4cd36080a5861b95ea 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,597 @@
+2020-10-06  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       Backported from master:
+       2020-10-06  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+       * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to
+       iterators.md.
+       (MVE_VLD_ST): Likewise.
+       (MVE_0): Likewise.
+       (MVE_1): Likewise.
+       (MVE_3): Likewise.
+       (MVE_2): Likewise.
+       (MVE_5): Likewise.
+       (MVE_6): Likewise.
+       (MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md.
+       (MVE_LANES): Likewise.
+       (MVE_constraint): Likewise.
+       (MVE_constraint1): Likewise.
+       (MVE_constraint2): Likewise.
+       (MVE_constraint3): Likewise.
+       (MVE_pred): Likewise.
+       (MVE_pred1): Likewise.
+       (MVE_pred2): Likewise.
+       (MVE_pred3): Likewise.
+       (MVE_B_ELEM): Likewise.
+       (MVE_H_ELEM): Likewise.
+       (V_sz_elem1): Likewise.
+       (V_extr_elem): Likewise.
+       (earlyclobber_32): Likewise.
+       (supf): Move int attribute from mve.md to iterators.md.
+       (mode1): Likewise.
+       (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md.
+       (VMVNQ_N): Likewise.
+       (VREV64Q): Likewise.
+       (VCVTQ_FROM_F): Likewise.
+       (VREV16Q): Likewise.
+       (VCVTAQ): Likewise.
+       (VMVNQ): Likewise.
+       (VDUPQ_N): Likewise.
+       (VCLZQ): Likewise.
+       (VADDVQ): Likewise.
+       (VREV32Q): Likewise.
+       (VMOVLBQ): Likewise.
+       (VMOVLTQ): Likewise.
+       (VCVTPQ): Likewise.
+       (VCVTNQ): Likewise.
+       (VCVTMQ): Likewise.
+       (VADDLVQ): Likewise.
+       (VCTPQ): Likewise.
+       (VCTPQ_M): Likewise.
+       (VCVTQ_N_TO_F): Likewise.
+       (VCREATEQ): Likewise.
+       (VSHRQ_N): Likewise.
+       (VCVTQ_N_FROM_F): Likewise.
+       (VADDLVQ_P): Likewise.
+       (VCMPNEQ): Likewise.
+       (VSHLQ): Likewise.
+       (VABDQ): Likewise.
+       (VADDQ_N): Likewise.
+       (VADDVAQ): Likewise.
+       (VADDVQ_P): Likewise.
+       (VANDQ): Likewise.
+       (VBICQ): Likewise.
+       (VBRSRQ_N): Likewise.
+       (VCADDQ_ROT270): Likewise.
+       (VCADDQ_ROT90): Likewise.
+       (VCMPEQQ): Likewise.
+       (VCMPEQQ_N): Likewise.
+       (VCMPNEQ_N): Likewise.
+       (VEORQ): Likewise.
+       (VHADDQ): Likewise.
+       (VHADDQ_N): Likewise.
+       (VHSUBQ): Likewise.
+       (VHSUBQ_N): Likewise.
+       (VMAXQ): Likewise.
+       (VMAXVQ): Likewise.
+       (VMINQ): Likewise.
+       (VMINVQ): Likewise.
+       (VMLADAVQ): Likewise.
+       (VMULHQ): Likewise.
+       (VMULLBQ_INT): Likewise.
+       (VMULLTQ_INT): Likewise.
+       (VMULQ): Likewise.
+       (VMULQ_N): Likewise.
+       (VORNQ): Likewise.
+       (VORRQ): Likewise.
+       (VQADDQ): Likewise.
+       (VQADDQ_N): Likewise.
+       (VQRSHLQ): Likewise.
+       (VQRSHLQ_N): Likewise.
+       (VQSHLQ): Likewise.
+       (VQSHLQ_N): Likewise.
+       (VQSHLQ_R): Likewise.
+       (VQSUBQ): Likewise.
+       (VQSUBQ_N): Likewise.
+       (VRHADDQ): Likewise.
+       (VRMULHQ): Likewise.
+       (VRSHLQ): Likewise.
+       (VRSHLQ_N): Likewise.
+       (VRSHRQ_N): Likewise.
+       (VSHLQ_N): Likewise.
+       (VSHLQ_R): Likewise.
+       (VSUBQ): Likewise.
+       (VSUBQ_N): Likewise.
+       (VADDLVAQ): Likewise.
+       (VBICQ_N): Likewise.
+       (VMLALDAVQ): Likewise.
+       (VMLALDAVXQ): Likewise.
+       (VMOVNBQ): Likewise.
+       (VMOVNTQ): Likewise.
+       (VORRQ_N): Likewise.
+       (VQMOVNBQ): Likewise.
+       (VQMOVNTQ): Likewise.
+       (VSHLLBQ_N): Likewise.
+       (VSHLLTQ_N): Likewise.
+       (VRMLALDAVHQ): Likewise.
+       (VBICQ_M_N): Likewise.
+       (VCVTAQ_M): Likewise.
+       (VCVTQ_M_TO_F): Likewise.
+       (VQRSHRNBQ_N): Likewise.
+       (VABAVQ): Likewise.
+       (VSHLCQ): Likewise.
+       (VRMLALDAVHAQ): Likewise.
+       (VADDVAQ_P): Likewise.
+       (VCLZQ_M): Likewise.
+       (VCMPEQQ_M_N): Likewise.
+       (VCMPEQQ_M): Likewise.
+       (VCMPNEQ_M_N): Likewise.
+       (VCMPNEQ_M): Likewise.
+       (VDUPQ_M_N): Likewise.
+       (VMAXVQ_P): Likewise.
+       (VMINVQ_P): Likewise.
+       (VMLADAVAQ): Likewise.
+       (VMLADAVQ_P): Likewise.
+       (VMLAQ_N): Likewise.
+       (VMLASQ_N): Likewise.
+       (VMVNQ_M): Likewise.
+       (VPSELQ): Likewise.
+       (VQDMLAHQ_N): Likewise.
+       (VQRDMLAHQ_N): Likewise.
+       (VQRDMLASHQ_N): Likewise.
+       (VQRSHLQ_M_N): Likewise.
+       (VQSHLQ_M_R): Likewise.
+       (VREV64Q_M): Likewise.
+       (VRSHLQ_M_N): Likewise.
+       (VSHLQ_M_R): Likewise.
+       (VSLIQ_N): Likewise.
+       (VSRIQ_N): Likewise.
+       (VMLALDAVQ_P): Likewise.
+       (VQMOVNBQ_M): Likewise.
+       (VMOVLTQ_M): Likewise.
+       (VMOVNBQ_M): Likewise.
+       (VRSHRNTQ_N): Likewise.
+       (VORRQ_M_N): Likewise.
+       (VREV32Q_M): Likewise.
+       (VREV16Q_M): Likewise.
+       (VQRSHRNTQ_N): Likewise.
+       (VMOVNTQ_M): Likewise.
+       (VMOVLBQ_M): Likewise.
+       (VMLALDAVAQ): Likewise.
+       (VQSHRNBQ_N): Likewise.
+       (VSHRNBQ_N): Likewise.
+       (VRSHRNBQ_N): Likewise.
+       (VMLALDAVXQ_P): Likewise.
+       (VQMOVNTQ_M): Likewise.
+       (VMVNQ_M_N): Likewise.
+       (VQSHRNTQ_N): Likewise.
+       (VMLALDAVAXQ): Likewise.
+       (VSHRNTQ_N): Likewise.
+       (VCVTMQ_M): Likewise.
+       (VCVTNQ_M): Likewise.
+       (VCVTPQ_M): Likewise.
+       (VCVTQ_M_N_FROM_F): Likewise.
+       (VCVTQ_M_FROM_F): Likewise.
+       (VRMLALDAVHQ_P): Likewise.
+       (VADDLVAQ_P): Likewise.
+       (VABAVQ_P): Likewise.
+       (VSHLQ_M): Likewise.
+       (VSRIQ_M_N): Likewise.
+       (VSUBQ_M): Likewise.
+       (VCVTQ_M_N_TO_F): Likewise.
+       (VHSUBQ_M): Likewise.
+       (VSLIQ_M_N): Likewise.
+       (VRSHLQ_M): Likewise.
+       (VMINQ_M): Likewise.
+       (VMULLBQ_INT_M): Likewise.
+       (VMULHQ_M): Likewise.
+       (VMULQ_M): Likewise.
+       (VHSUBQ_M_N): Likewise.
+       (VHADDQ_M_N): Likewise.
+       (VORRQ_M): Likewise.
+       (VRMULHQ_M): Likewise.
+       (VQADDQ_M): Likewise.
+       (VRSHRQ_M_N): Likewise.
+       (VQSUBQ_M_N): Likewise.
+       (VADDQ_M): Likewise.
+       (VORNQ_M): Likewise.
+       (VRHADDQ_M): Likewise.
+       (VQSHLQ_M): Likewise.
+       (VANDQ_M): Likewise.
+       (VBICQ_M): Likewise.
+       (VSHLQ_M_N): Likewise.
+       (VCADDQ_ROT270_M): Likewise.
+       (VQRSHLQ_M): Likewise.
+       (VQADDQ_M_N): Likewise.
+       (VADDQ_M_N): Likewise.
+       (VMAXQ_M): Likewise.
+       (VQSUBQ_M): Likewise.
+       (VMLASQ_M_N): Likewise.
+       (VMLADAVAQ_P): Likewise.
+       (VBRSRQ_M_N): Likewise.
+       (VMULQ_M_N): Likewise.
+       (VCADDQ_ROT90_M): Likewise.
+       (VMULLTQ_INT_M): Likewise.
+       (VEORQ_M): Likewise.
+       (VSHRQ_M_N): Likewise.
+       (VSUBQ_M_N): Likewise.
+       (VHADDQ_M): Likewise.
+       (VABDQ_M): Likewise.
+       (VMLAQ_M_N): Likewise.
+       (VQSHLQ_M_N): Likewise.
+       (VMLALDAVAQ_P): Likewise.
+       (VMLALDAVAXQ_P): Likewise.
+       (VQRSHRNBQ_M_N): Likewise.
+       (VQRSHRNTQ_M_N): Likewise.
+       (VQSHRNBQ_M_N): Likewise.
+       (VQSHRNTQ_M_N): Likewise.
+       (VRSHRNBQ_M_N): Likewise.
+       (VRSHRNTQ_M_N): Likewise.
+       (VSHLLBQ_M_N): Likewise.
+       (VSHLLTQ_M_N): Likewise.
+       (VSHRNBQ_M_N): Likewise.
+       (VSHRNTQ_M_N): Likewise.
+       (VSTRWSBQ): Likewise.
+       (VSTRBSOQ): Likewise.
+       (VSTRBQ): Likewise.
+       (VLDRBGOQ): Likewise.
+       (VLDRBQ): Likewise.
+       (VLDRWGBQ): Likewise.
+       (VLD1Q): Likewise.
+       (VLDRHGOQ): Likewise.
+       (VLDRHGSOQ): Likewise.
+       (VLDRHQ): Likewise.
+       (VLDRWQ): Likewise.
+       (VLDRDGBQ): Likewise.
+       (VLDRDGOQ): Likewise.
+       (VLDRDGSOQ): Likewise.
+       (VLDRWGOQ): Likewise.
+       (VLDRWGSOQ): Likewise.
+       (VST1Q): Likewise.
+       (VSTRHSOQ): Likewise.
+       (VSTRHSSOQ): Likewise.
+       (VSTRHQ): Likewise.
+       (VSTRWQ): Likewise.
+       (VSTRDSBQ): Likewise.
+       (VSTRDSOQ): Likewise.
+       (VSTRDSSOQ): Likewise.
+       (VSTRWSOQ): Likewise.
+       (VSTRWSSOQ): Likewise.
+       (VSTRWSBWBQ): Likewise.
+       (VLDRWGBWBQ): Likewise.
+       (VSTRDSBWBQ): Likewise.
+       (VLDRDGBWBQ): Likewise.
+       (VADCIQ): Likewise.
+       (VADCIQ_M): Likewise.
+       (VSBCQ): Likewise.
+       (VSBCQ_M): Likewise.
+       (VSBCIQ): Likewise.
+       (VSBCIQ_M): Likewise.
+       (VADCQ): Likewise.
+       (VADCQ_M): Likewise.
+       (UQRSHLLQ): Likewise.
+       (SQRSHRLQ): Likewise.
+       (VSHLCQ_M): Likewise.
+       * config/arm/mve.md (MVE_types): Move mode iterator to iterators.md from mve.md.
+       (MVE_VLD_ST): Likewise.
+       (MVE_0): Likewise.
+       (MVE_1): Likewise.
+       (MVE_3): Likewise.
+       (MVE_2): Likewise.
+       (MVE_5): Likewise.
+       (MVE_6): Likewise.
+       (MVE_CNVT): Move mode attribute iterator to iterators.md from mve.md.
+       (MVE_LANES): Likewise.
+       (MVE_constraint): Likewise.
+       (MVE_constraint1): Likewise.
+       (MVE_constraint2): Likewise.
+       (MVE_constraint3): Likewise.
+       (MVE_pred): Likewise.
+       (MVE_pred1): Likewise.
+       (MVE_pred2): Likewise.
+       (MVE_pred3): Likewise.
+       (MVE_B_ELEM): Likewise.
+       (MVE_H_ELEM): Likewise.
+       (V_sz_elem1): Likewise.
+       (V_extr_elem): Likewise.
+       (earlyclobber_32): Likewise.
+       (supf): Move int attribute to iterators.md from mve.md.
+       (mode1): Likewise.
+       (VCVTQ_TO_F): Move int iterator to iterators.md from mve.md.
+       (VMVNQ_N): Likewise.
+       (VREV64Q): Likewise.
+       (VCVTQ_FROM_F): Likewise.
+       (VREV16Q): Likewise.
+       (VCVTAQ): Likewise.
+       (VMVNQ): Likewise.
+       (VDUPQ_N): Likewise.
+       (VCLZQ): Likewise.
+       (VADDVQ): Likewise.
+       (VREV32Q): Likewise.
+       (VMOVLBQ): Likewise.
+       (VMOVLTQ): Likewise.
+       (VCVTPQ): Likewise.
+       (VCVTNQ): Likewise.
+       (VCVTMQ): Likewise.
+       (VADDLVQ): Likewise.
+       (VCTPQ): Likewise.
+       (VCTPQ_M): Likewise.
+       (VCVTQ_N_TO_F): Likewise.
+       (VCREATEQ): Likewise.
+       (VSHRQ_N): Likewise.
+       (VCVTQ_N_FROM_F): Likewise.
+       (VADDLVQ_P): Likewise.
+       (VCMPNEQ): Likewise.
+       (VSHLQ): Likewise.
+       (VABDQ): Likewise.
+       (VADDQ_N): Likewise.
+       (VADDVAQ): Likewise.
+       (VADDVQ_P): Likewise.
+       (VANDQ): Likewise.
+       (VBICQ): Likewise.
+       (VBRSRQ_N): Likewise.
+       (VCADDQ_ROT270): Likewise.
+       (VCADDQ_ROT90): Likewise.
+       (VCMPEQQ): Likewise.
+       (VCMPEQQ_N): Likewise.
+       (VCMPNEQ_N): Likewise.
+       (VEORQ): Likewise.
+       (VHADDQ): Likewise.
+       (VHADDQ_N): Likewise.
+       (VHSUBQ): Likewise.
+       (VHSUBQ_N): Likewise.
+       (VMAXQ): Likewise.
+       (VMAXVQ): Likewise.
+       (VMINQ): Likewise.
+       (VMINVQ): Likewise.
+       (VMLADAVQ): Likewise.
+       (VMULHQ): Likewise.
+       (VMULLBQ_INT): Likewise.
+       (VMULLTQ_INT): Likewise.
+       (VMULQ): Likewise.
+       (VMULQ_N): Likewise.
+       (VORNQ): Likewise.
+       (VORRQ): Likewise.
+       (VQADDQ): Likewise.
+       (VQADDQ_N): Likewise.
+       (VQRSHLQ): Likewise.
+       (VQRSHLQ_N): Likewise.
+       (VQSHLQ): Likewise.
+       (VQSHLQ_N): Likewise.
+       (VQSHLQ_R): Likewise.
+       (VQSUBQ): Likewise.
+       (VQSUBQ_N): Likewise.
+       (VRHADDQ): Likewise.
+       (VRMULHQ): Likewise.
+       (VRSHLQ): Likewise.
+       (VRSHLQ_N): Likewise.
+       (VRSHRQ_N): Likewise.
+       (VSHLQ_N): Likewise.
+       (VSHLQ_R): Likewise.
+       (VSUBQ): Likewise.
+       (VSUBQ_N): Likewise.
+       (VADDLVAQ): Likewise.
+       (VBICQ_N): Likewise.
+       (VMLALDAVQ): Likewise.
+       (VMLALDAVXQ): Likewise.
+       (VMOVNBQ): Likewise.
+       (VMOVNTQ): Likewise.
+       (VORRQ_N): Likewise.
+       (VQMOVNBQ): Likewise.
+       (VQMOVNTQ): Likewise.
+       (VSHLLBQ_N): Likewise.
+       (VSHLLTQ_N): Likewise.
+       (VRMLALDAVHQ): Likewise.
+       (VBICQ_M_N): Likewise.
+       (VCVTAQ_M): Likewise.
+       (VCVTQ_M_TO_F): Likewise.
+       (VQRSHRNBQ_N): Likewise.
+       (VABAVQ): Likewise.
+       (VSHLCQ): Likewise.
+       (VRMLALDAVHAQ): Likewise.
+       (VADDVAQ_P): Likewise.
+       (VCLZQ_M): Likewise.
+       (VCMPEQQ_M_N): Likewise.
+       (VCMPEQQ_M): Likewise.
+       (VCMPNEQ_M_N): Likewise.
+       (VCMPNEQ_M): Likewise.
+       (VDUPQ_M_N): Likewise.
+       (VMAXVQ_P): Likewise.
+       (VMINVQ_P): Likewise.
+       (VMLADAVAQ): Likewise.
+       (VMLADAVQ_P): Likewise.
+       (VMLAQ_N): Likewise.
+       (VMLASQ_N): Likewise.
+       (VMVNQ_M): Likewise.
+       (VPSELQ): Likewise.
+       (VQDMLAHQ_N): Likewise.
+       (VQRDMLAHQ_N): Likewise.
+       (VQRDMLASHQ_N): Likewise.
+       (VQRSHLQ_M_N): Likewise.
+       (VQSHLQ_M_R): Likewise.
+       (VREV64Q_M): Likewise.
+       (VRSHLQ_M_N): Likewise.
+       (VSHLQ_M_R): Likewise.
+       (VSLIQ_N): Likewise.
+       (VSRIQ_N): Likewise.
+       (VMLALDAVQ_P): Likewise.
+       (VQMOVNBQ_M): Likewise.
+       (VMOVLTQ_M): Likewise.
+       (VMOVNBQ_M): Likewise.
+       (VRSHRNTQ_N): Likewise.
+       (VORRQ_M_N): Likewise.
+       (VREV32Q_M): Likewise.
+       (VREV16Q_M): Likewise.
+       (VQRSHRNTQ_N): Likewise.
+       (VMOVNTQ_M): Likewise.
+       (VMOVLBQ_M): Likewise.
+       (VMLALDAVAQ): Likewise.
+       (VQSHRNBQ_N): Likewise.
+       (VSHRNBQ_N): Likewise.
+       (VRSHRNBQ_N): Likewise.
+       (VMLALDAVXQ_P): Likewise.
+       (VQMOVNTQ_M): Likewise.
+       (VMVNQ_M_N): Likewise.
+       (VQSHRNTQ_N): Likewise.
+       (VMLALDAVAXQ): Likewise.
+       (VSHRNTQ_N): Likewise.
+       (VCVTMQ_M): Likewise.
+       (VCVTNQ_M): Likewise.
+       (VCVTPQ_M): Likewise.
+       (VCVTQ_M_N_FROM_F): Likewise.
+       (VCVTQ_M_FROM_F): Likewise.
+       (VRMLALDAVHQ_P): Likewise.
+       (VADDLVAQ_P): Likewise.
+       (VABAVQ_P): Likewise.
+       (VSHLQ_M): Likewise.
+       (VSRIQ_M_N): Likewise.
+       (VSUBQ_M): Likewise.
+       (VCVTQ_M_N_TO_F): Likewise.
+       (VHSUBQ_M): Likewise.
+       (VSLIQ_M_N): Likewise.
+       (VRSHLQ_M): Likewise.
+       (VMINQ_M): Likewise.
+       (VMULLBQ_INT_M): Likewise.
+       (VMULHQ_M): Likewise.
+       (VMULQ_M): Likewise.
+       (VHSUBQ_M_N): Likewise.
+       (VHADDQ_M_N): Likewise.
+       (VORRQ_M): Likewise.
+       (VRMULHQ_M): Likewise.
+       (VQADDQ_M): Likewise.
+       (VRSHRQ_M_N): Likewise.
+       (VQSUBQ_M_N): Likewise.
+       (VADDQ_M): Likewise.
+       (VORNQ_M): Likewise.
+       (VRHADDQ_M): Likewise.
+       (VQSHLQ_M): Likewise.
+       (VANDQ_M): Likewise.
+       (VBICQ_M): Likewise.
+       (VSHLQ_M_N): Likewise.
+       (VCADDQ_ROT270_M): Likewise.
+       (VQRSHLQ_M): Likewise.
+       (VQADDQ_M_N): Likewise.
+       (VADDQ_M_N): Likewise.
+       (VMAXQ_M): Likewise.
+       (VQSUBQ_M): Likewise.
+       (VMLASQ_M_N): Likewise.
+       (VMLADAVAQ_P): Likewise.
+       (VBRSRQ_M_N): Likewise.
+       (VMULQ_M_N): Likewise.
+       (VCADDQ_ROT90_M): Likewise.
+       (VMULLTQ_INT_M): Likewise.
+       (VEORQ_M): Likewise.
+       (VSHRQ_M_N): Likewise.
+       (VSUBQ_M_N): Likewise.
+       (VHADDQ_M): Likewise.
+       (VABDQ_M): Likewise.
+       (VMLAQ_M_N): Likewise.
+       (VQSHLQ_M_N): Likewise.
+       (VMLALDAVAQ_P): Likewise.
+       (VMLALDAVAXQ_P): Likewise.
+       (VQRSHRNBQ_M_N): Likewise.
+       (VQRSHRNTQ_M_N): Likewise.
+       (VQSHRNBQ_M_N): Likewise.
+       (VQSHRNTQ_M_N): Likewise.
+       (VRSHRNBQ_M_N): Likewise.
+       (VRSHRNTQ_M_N): Likewise.
+       (VSHLLBQ_M_N): Likewise.
+       (VSHLLTQ_M_N): Likewise.
+       (VSHRNBQ_M_N): Likewise.
+       (VSHRNTQ_M_N): Likewise.
+       (VSTRWSBQ): Likewise.
+       (VSTRBSOQ): Likewise.
+       (VSTRBQ): Likewise.
+       (VLDRBGOQ): Likewise.
+       (VLDRBQ): Likewise.
+       (VLDRWGBQ): Likewise.
+       (VLD1Q): Likewise.
+       (VLDRHGOQ): Likewise.
+       (VLDRHGSOQ): Likewise.
+       (VLDRHQ): Likewise.
+       (VLDRWQ): Likewise.
+       (VLDRDGBQ): Likewise.
+       (VLDRDGOQ): Likewise.
+       (VLDRDGSOQ): Likewise.
+       (VLDRWGOQ): Likewise.
+       (VLDRWGSOQ): Likewise.
+       (VST1Q): Likewise.
+       (VSTRHSOQ): Likewise.
+       (VSTRHSSOQ): Likewise.
+       (VSTRHQ): Likewise.
+       (VSTRWQ): Likewise.
+       (VSTRDSBQ): Likewise.
+       (VSTRDSOQ): Likewise.
+       (VSTRDSSOQ): Likewise.
+       (VSTRWSOQ): Likewise.
+       (VSTRWSSOQ): Likewise.
+       (VSTRWSBWBQ): Likewise.
+       (VLDRWGBWBQ): Likewise.
+       (VSTRDSBWBQ): Likewise.
+       (VLDRDGBWBQ): Likewise.
+       (VADCIQ): Likewise.
+       (VADCIQ_M): Likewise.
+       (VSBCQ): Likewise.
+       (VSBCQ_M): Likewise.
+       (VSBCIQ): Likewise.
+       (VSBCIQ_M): Likewise.
+       (VADCQ): Likewise.
+       (VADCQ_M): Likewise.
+       (UQRSHLLQ): Likewise.
+       (SQRSHRLQ): Likewise.
+       (VSHLCQ_M): Likewise.
+       (define_c_enum "unspec"): Move MVE enumerator to unspecs.md from mve.md.
+       * config/arm/unspecs.md (define_c_enum "unspec"): Move MVE enumerator from
+       mve.md to unspecs.md.
+
+2020-10-06  Joe Ramsay  <Joe.Ramsay@arm.com>
+
+       Backported from master:
+       2020-10-02  Joe Ramsay  <joe.ramsay@arm.com>
+
+       * config/arm/arm_mve.h (__arm_vmaxnmavq): Remove coercion of scalar
+       argument.
+       (__arm_vmaxnmvq): Likewise.
+       (__arm_vminnmavq): Likewise.
+       (__arm_vminnmvq): Likewise.
+       (__arm_vmaxnmavq_p): Likewise.
+       (__arm_vmaxnmvq_p): Likewise (and delete duplicate definition).
+       (__arm_vminnmavq_p): Likewise.
+       (__arm_vminnmvq_p): Likewise.
+       (__arm_vmaxavq): Likewise.
+       (__arm_vmaxavq_p): Likewise.
+       (__arm_vmaxvq): Likewise.
+       (__arm_vmaxvq_p): Likewise.
+       (__arm_vminavq): Likewise.
+       (__arm_vminavq_p): Likewise.
+       (__arm_vminvq): Likewise.
+       (__arm_vminvq_p): Likewise.
+
+2020-10-06  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/97236
+       * tree-vect-stmts.c (get_group_load_store_type): Keep
+       VMAT_ELEMENTWISE for single-element vectors.
+
+2020-10-06  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       Backported from master:
+       2020-10-06  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * doc/invoke.texi: Add z15/arch13 to the list of documented
+       -march/-mtune options.
+
+2020-10-06  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       Backported from master:
+       2020-08-12  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       PR target/96456
+       * config/s390/s390.h (TARGET_NONSIGNALING_VECTOR_COMPARE_OK): New
+       macro.
+       * config/s390/vector.md (vcond_comparison_operator): Use new macro
+       for the check.
+
 2020-10-05  Alex Coplan  <alex.coplan@arm.com>
 
        * config/arm/arm-cpus.in (neoverse-v1): Add missing vendor and

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 684bf4bc84dafebc61632769411a23d6ac8666c8..8478d98f282f206a1657278249810e715a52133e 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20201006
+20201007

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 16e5766cc2c2fd624ef04ef5111bfd2b7146ae65..97e914b372de68c2194035dedbb0dcbd5181fad3 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,75 @@
+2020-10-06  Joe Ramsay  <Joe.Ramsay@arm.com>
+
+       Backported from master:
+       2020-10-02  Joe Ramsay  <Joe.Ramsay@arm.com>
+
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Add test for mismatched
+       width of scalar argument.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise.
+
+2020-10-06  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/97236
+       * gcc.dg/vect/pr97236.c: New testcase.
+
+2020-10-06  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       Backported from master:
+       2020-08-12  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       PR target/96456
+       * gcc.target/s390/pr96456.c: New test.
+
 2020-10-05  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from master:

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index c2054dfcb9170557e306572ccdb63cf31b0ce0ec..e356f6ae655f4a0ae4010d35fa70ba78f926196d 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,15 @@
+2020-10-06  Patrick Palka  <ppalka@redhat.com>
+
+       Backported from master:
+       2020-10-02  Patrick Palka  <ppalka@redhat.com>
+
+       * include/bits/stl_iterator.h (reverse_iterator::iter_move):
+       Define for C++20 as per P0896.
+       (reverse_iterator::iter_swap): Likewise.
+       (move_iterator::operator*): Apply P0896 changes for C++20.
+       (move_iterator::operator[]): Likewise.
+       * testsuite/24_iterators/reverse_iterator/cust.cc: New test.
+
 2020-09-22  Jonathan Wakely  <jwakely@redhat.com>
 
        Backported from master: