i386.md (prefetch): Fix for 64bit mode.

	* i386.md (prefetch): Fix for 64bit mode.
	(prefetch_sse_rex, prefetch_3dnow_rex): New patterns.

From-SVN: r56455

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c1c0c7c675cc998bd6ee26db1e8b99e13b57b5aa..2b372262fccf4d987c9cc19aaee4033928c1972f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2002-08-20  Andreas Jaeger  <aj@suse.de>
 
+       Merge from trunk:
+       Wed Jul 17 00:20:48 CEST 2002  Jan Hubicka  <jh@suse.cz>
+
+       * i386.md (prefetch): Fix for 64bit mode.
+       (prefetch_sse_rex, prefetch_3dnow_rex): New patterns.
+
+       2002-08-11  Andreas Jaeger  <aj@suse.de>
        PR target/7531:
        * doc/invoke.texi (i386 and x86-64 Options): Document -mcmodel.
 
@@ -189,7 +196,7 @@
                instead of gen_rtx_SUBREG.
                (arm_reload_out_hi): Use gen_lowpart instead of
                gen_rtx_SUBREG to access QImode components.
-               * config/arm/arm.md: Disable zero_extend split for QImode 
+               * config/arm/arm.md: Disable zero_extend split for QImode
                subregs in BIG_ENDIAN mode.
                (storehi_bigend): Match use of least significant byte.
                (storeinthi): Remove extraneous SUBREG.
@@ -275,7 +282,7 @@
 
        * config/m68hc11/m68hc11.md ("*movqi_68hc12"): Avoid allocating
        QI mode registers in soft registers.
-       ("zero_extendqihi2"): Do not take into account soft registers 
+       ("zero_extendqihi2"): Do not take into account soft registers
        for register allocation (use '*' constraint).
 
 2002-07-05  Stephane Carrez  <stcarrez@nerim.fr>
@@ -296,7 +303,7 @@
        * dwarfout.c (output_reg_number): Fix warning message.
        (output_bound_representation): Check SAVE_EXPR_RTL is not NULL
        before using it.
-       
+
 2002-07-03  Richard Henderson  <rth@redhat.com>
 
        * config/i386/i386.md (prologue_get_pc): Issue pop here ...
@@ -339,7 +346,7 @@
        * config/m68hc11/m68hc11.md ("*addsi3"): Use 'o' constraint to
        avoid the auto increment addressing modes.
        ("*subsi3"): Likewise.
-       (split for add/sub on address): For 68HC12 push the value on 
+       (split for add/sub on address): For 68HC12 push the value on
        the stack and do the operation with a pop.
 
 2002-06-28  Stephane Carrez  <stcarrez@nerim.fr>
@@ -386,7 +393,7 @@
 
        * config/xtensa/xtensa.h (ASM_OUTPUT_POOL_PROLOGUE): Pass
        flag_function_sections as new 3rd arg to resolve_unique_section.
-       
+
 2002-06-27  Neil Booth  <neil@daikokuya.co.uk>
 
        PR preprocessor/7070
@@ -402,7 +409,7 @@
        * doc/install.texi: Change ` bit' to `-bit'.
        * doc/md.texi: Change `-bits' to `-bit'.
        * doc/tm.texi: Change `-bits' to ` bits'.
-       
+
 2002-06-24  David S. Miller  <davem@redhat.com>
 
        * config/sparc/sparc.h (INIT_TARGET_OPTABS): If ARCH64, set the

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c1a4eb980740d7600bea120d2d3b0b2971b09ef9..4275675ce159ebf188c511c2f3ba0f2717f705b7 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -19783,7 +19783,7 @@
   [(set_attr "type" "mmx")])
 
 (define_expand "prefetch"
-  [(prefetch (match_operand:SI 0 "address_operand" "")
+  [(prefetch (match_operand 0 "address_operand" "")
             (match_operand:SI 1 "const_int_operand" "")
             (match_operand:SI 2 "const_int_operand" ""))]
   "TARGET_PREFETCH_SSE || TARGET_3DNOW"
@@ -19795,6 +19795,8 @@
     abort ();
   if (locality < 0 || locality > 3)
     abort ();
+  if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
+    abort ();
 
   /* Use 3dNOW prefetch in case we are asking for write prefetch not
      suported by SSE counterpart or the SSE prefetch is not available
@@ -19810,7 +19812,26 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
             (const_int 0)
             (match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_PREFETCH_SSE"
+  "TARGET_PREFETCH_SSE && !TARGET_64BIT"
+{
+  static const char * const patterns[4] = {
+   "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+  };
+
+  int locality = INTVAL (operands[1]);
+  if (locality < 0 || locality > 3)
+    abort ();
+
+  return patterns[locality];  
+}
+  [(set_attr "type" "sse")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_sse_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+            (const_int 0)
+            (match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_PREFETCH_SSE && TARGET_64BIT"
 {
   static const char * const patterns[4] = {
    "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
@@ -19828,7 +19849,21 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
             (match_operand:SI 1 "const_int_operand" "n")
             (const_int 3))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW && !TARGET_64BIT"
+{
+  if (INTVAL (operands[1]) == 0)
+    return "prefetch\t%a0";
+  else
+    return "prefetchw\t%a0";
+}
+  [(set_attr "type" "mmx")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_3dnow_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+            (match_operand:SI 1 "const_int_operand" "n")
+            (const_int 3))]
+  "TARGET_3DNOW && TARGET_64BIT"
 {
   if (INTVAL (operands[1]) == 0)
     return "prefetch\t%a0";