arm64: dts: renesas: r8a779g0: Describe PCIe root ports

Add nodes which describe the root ports in the PCIe controller DT nodes.
This can be used together with the pwrctrl driver to control clock and
power supply to a PCIe slot.  For example usage, refer to the Sparrow
Hawk board.

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/20250607194541.79176-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 6dbf05a559357170984295af6190266881d12f86..8d9ca30c299c918e5ab5c4cda3699419e5259821 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -798,6 +798,16 @@
                                        <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
                        snps,enable-cdm-check;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec0_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                pciec1: pcie@e65d8000 {
@@ -835,6 +845,16 @@
                                        <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
                        snps,enable-cdm-check;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec1_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                pciec0_ep: pcie-ep@e65d0000 {