reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ

On i.MX8MQ, the MIPI CSI reset lines are active-low and not self-clearing.
Writing '0' asserts reset and it remains asserted until explicitly
deasserted by software.

This driver previously treated the MIPI CSI reset signals as active-high,
which led to incorrect reset assert/deassert sequencing. This issue was
exposed by commit 6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly
release reset").

Fix this by reflecting the correct reset polarity and ensuring proper
reset handling.

Fixes: c979dbf59987 ("reset: imx7: Add support for i.MX8MQ IP block variant")
Cc: stable@vger.kernel.org # 6d79bb8fd2aa: media: imx8mq-mipi-csi2: Explicitly release reset
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index dd01fe11c5cb38572079750cda968270cf25780e..a3cb8244d76a6f71473b562da6b0ecc877192de7 100644 (file)
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -236,6 +236,12 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
 
        case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
        case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
+       case IMX8MQ_RESET_MIPI_CSI1_CORE_RESET:
+       case IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET:
+       case IMX8MQ_RESET_MIPI_CSI1_ESC_RESET:
+       case IMX8MQ_RESET_MIPI_CSI2_CORE_RESET:
+       case IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET:
+       case IMX8MQ_RESET_MIPI_CSI2_ESC_RESET:
        case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
        case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
        case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: