cb_data->kaddr1 = &res.a1;
cb_data->kaddr2 = &res.a2;
break;
+ case COMMAND_SMC_ATF_BUILD_VER:
+ cb_data->status = BIT(SVC_STATUS_OK);
+ cb_data->kaddr1 = &res.a1;
+ cb_data->kaddr2 = &res.a2;
+ cb_data->kaddr3 = &res.a3;
+ break;
case COMMAND_RSU_DCMF_VERSION:
cb_data->status = BIT(SVC_STATUS_OK);
cb_data->kaddr1 = &res.a1;
a1 = 0;
a2 = 0;
break;
+ case COMMAND_SMC_ATF_BUILD_VER:
+ a0 = INTEL_SIP_SMC_ATF_BUILD_VER;
+ a1 = 0;
+ a2 = 0;
+ a3 = 0;
+ break;
case COMMAND_MBOX_SEND_CMD:
a0 = INTEL_SIP_SMC_MBOX_SEND_CMD;
a1 = pdata->arg[0];
#define INTEL_SIP_SMC_SVC_VERSION \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_SVC_FUNCID_VERSION)
+/**
+ * Request INTEL_SIP_SMC_ATF_BUILD_VER
+ *
+ * Sync call used to query the ATF Build Version
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_ATF_BUILD_VER
+ * a1-a7 not used
+ *
+ * Return status:
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ * a1 Major
+ * a2 Minor
+ * a3 Patch
+ */
+#define INTEL_SIP_SMC_ATF_BUILD_VERSION 155
+#define INTEL_SIP_SMC_ATF_BUILD_VER \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_ATF_BUILD_VERSION)
+
/**
* SMC call protocol for FPGA Crypto Service (FCS)
* FUNCID starts from 90
*
* @COMMAND_HWMON_READVOLT: query the voltage from the hardware monitor,
* return status is SVC_STATUS_OK or SVC_STATUS_ERROR
+ *
+ * @COMMAND_SMC_ATF_BUILD_VER: Non-mailbox SMC ATF Build Version,
+ * return status is SVC_STATUS_OK
+ *
*/
enum stratix10_svc_command_code {
/* for FPGA */
COMMAND_SMC_SVC_VERSION = 200,
/* for HWMON */
COMMAND_HWMON_READTEMP,
- COMMAND_HWMON_READVOLT
+ COMMAND_HWMON_READVOLT,
+ COMMAND_SMC_ATF_BUILD_VER
};
/**