[AArch64] Fix PR81800

PR81800 is about the lrint inline giving spurious FE_INEXACT exceptions.
The previous change for PR81800 didn't fix this: when lrint is disabled
in the backend, the midend will simply use llrint.  This actually makes
things worse since llrint now also ignores FE_INVALID exceptions!
The fix is to disable lrint/llrint on double if the size of a long is
smaller (ie. ilp32).

    gcc/
	PR target/81800
	* gcc/config/aarch64/aarch64.md (lrint): Disable lrint pattern if GPF
	operand is larger than a long int.

    testsuite/
	PR target/81800
	* gcc.target/aarch64/no-inline-lrint_3.c: New test.

From-SVN: r275373

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f362c3634c9ee0c6610a500d514eeb5ed45127cb..26d9923808f2063765c2504cea1060c32db11f56 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-09-04  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backport from mainline
+       2019-08-13  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       PR target/81800
+       * gcc/config/aarch64/aarch64.md (lrint): Disable lrint pattern if GPF
+       operand is larger than a long int.
+
 2019-09-03  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/91597

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5a1894063a1ed2db1cc947c9c449d48808ed96ae..f08cd0930b3fc6527fbca218ad3c464f1ead0103 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6304,7 +6304,7 @@
   [(match_operand:GPI 0 "register_operand")
    (match_operand:GPF 1 "register_operand")]
   "TARGET_FLOAT
-   && ((GET_MODE_SIZE (<GPF:MODE>mode) <= GET_MODE_SIZE (<GPI:MODE>mode))
+   && ((GET_MODE_BITSIZE (<GPF:MODE>mode) <= LONG_TYPE_SIZE)
    || !flag_trapping_math || flag_fp_int_builtin_inexact)"
 {
   rtx cvt = gen_reg_rtx (<GPF:MODE>mode);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5b6958ceabd1cba3bd20f1be81b60cbf4991e010..70387abaa8ed65e68dff4c6a49a7391ea391a5cf 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2019-09-04  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backport from mainline
+       2019-08-13  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       PR target/81800
+       * gcc.target/aarch64/no-inline-lrint_3.c: New test.
+
 2019-09-03  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/91597

diff --git a/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c
new file mode 100644 (file)
index 0000000..ca772cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/no-inline-lrint_3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O3 -fno-math-errno -fno-fp-int-builtin-inexact" } */
+
+#define TEST(name, float_type, int_type, fn) void f_##name (float_type x) \
+{                                                                        \
+  volatile int_type   b = __builtin_##fn (x);                            \
+}
+
+TEST (dld, double, long, lrint)
+TEST (flf, float , long, lrintf)
+
+TEST (did, double, int, lrint)
+TEST (fif, float , int, lrintf)
+
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, \[d,s\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "bl\tlrint" 2 } } */