drm/amdgpu: move read_indexed_register to amdgpu_reg_access

The read_indexed_register helper is duplicated across multiple files
with identical logic.

Move it to amdgpu_reg_access.c as
amdgpu_read_indexed_register and update all users accordingly.

No functional changes intended.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Gabriel Almeida <gabrielsousa230@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
index 540040c76058b2f3b5a5d5cf5d61220aa2e47824..daefbeeee4d2c5434c45bf602d97ba1b783054c4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
@@ -956,3 +956,21 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
        }
        return ret;
 }
+
+
+uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev,
+                              u32 se_num, u32 sh_num, u32 reg_offset)
+{
+       uint32_t val;
+
+       mutex_lock(&adev->grbm_idx_mutex);
+       if (se_num != 0xffffffff || sh_num != 0xffffffff)
+               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
+
+       val = RREG32(reg_offset);
+
+       if (se_num != 0xffffffff || sh_num != 0xffffffff)
+               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
+       mutex_unlock(&adev->grbm_idx_mutex);
+       return val;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
index 4d88e5cd19fc9129945cc20f52a177ae03146806..a1011af6b52b40b2fe558cb954401950ad155047 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
@@ -160,4 +160,7 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
                                    uint32_t reg_addr, char reg_name[],
                                    uint32_t expected_value, uint32_t mask);
 
+uint32_t amdgpu_read_indexed_register(struct amdgpu_device *adev,
+                                       u32 se_num, u32 sh_num, u32 reg_offset);
+
 #endif /* __AMDGPU_REG_ACCESS_H__ */

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 030d8066494cf32c553874afb2de7a012dfb244d..72edf5326b05ba3492ef20b6ed77fc45d10e717d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -354,29 +354,12 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
        { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 };
 
-static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
-                                        u32 sh_num, u32 reg_offset)
-{
-       uint32_t val;
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
-
-       val = RREG32(reg_offset);
-
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
-       mutex_unlock(&adev->grbm_idx_mutex);
-       return val;
-}
-
 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
                                      bool indexed, u32 se_num,
                                      u32 sh_num, u32 reg_offset)
 {
        if (indexed) {
-               return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+               return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
        } else {
                if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
                        return adev->gfx.config.gb_addr_config;

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 27bcbbae5db458bf44f17bb26fa5a3507235f0e3..87b398dd0769bdd9203960260d75e98201ce912f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -401,29 +401,12 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
        { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 };
 
-static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
-                                        u32 sh_num, u32 reg_offset)
-{
-       uint32_t val;
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
-
-       val = RREG32(reg_offset);
-
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
-       mutex_unlock(&adev->grbm_idx_mutex);
-       return val;
-}
-
 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
                                         bool indexed, u32 se_num,
                                         u32 sh_num, u32 reg_offset)
 {
        if (indexed) {
-               return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+               return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
        } else {
                if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
                        return adev->gfx.config.gb_addr_config;

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 7e4353d0ce6e306d0a85dbdf358146d81a07c0d4..93c002e511c7d21673ff1496e019a10d6d93b953 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -306,29 +306,12 @@ static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
        { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
 };
 
-static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
-                                        u32 sh_num, u32 reg_offset)
-{
-       uint32_t val;
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
-
-       val = RREG32(reg_offset);
-
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
-       mutex_unlock(&adev->grbm_idx_mutex);
-       return val;
-}
-
 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
                                      bool indexed, u32 se_num,
                                      u32 sh_num, u32 reg_offset)
 {
        if (indexed) {
-               return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
+               return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
        } else {
                if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
                        return adev->gfx.config.gb_addr_config;

diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index d1adf19a51c4507a77a3b595b7e0cec75ece52c9..265db9331d0bbed06d3274d6ef3c8ff361269f6b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -132,31 +132,12 @@ static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {
        { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
 };
 
-static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,
-                                           u32 se_num,
-                                           u32 sh_num,
-                                           u32 reg_offset)
-{
-       uint32_t val;
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
-
-       val = RREG32(reg_offset);
-
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
-       mutex_unlock(&adev->grbm_idx_mutex);
-       return val;
-}
-
 static uint32_t soc24_get_register_value(struct amdgpu_device *adev,
                                         bool indexed, u32 se_num,
                                         u32 sh_num, u32 reg_offset)
 {
        if (indexed) {
-               return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);
+               return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
        } else {
                if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&
                    adev->gfx.config.gb_addr_config)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
index e88bebd928efffd6d0c5a94bbf5705b3e804f532..5f05c8e68297b9f565c6123186f38674acba31c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
@@ -184,31 +184,13 @@ static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = {
        { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) },
 };
 
-static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev,
-                                              u32 se_num,
-                                              u32 sh_num,
-                                              u32 reg_offset)
-{
-       uint32_t val;
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
-
-       val = RREG32(reg_offset);
-
-       if (se_num != 0xffffffff || sh_num != 0xffffffff)
-               amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
-       mutex_unlock(&adev->grbm_idx_mutex);
-       return val;
-}
 
 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev,
                                            bool indexed, u32 se_num,
                                            u32 sh_num, u32 reg_offset)
 {
        if (indexed) {
-               return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset);
+               return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
        } else {
                if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) &&
                    adev->gfx.config.gb_addr_config)