arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0

Add pin control configuration for the ETH0 Ethernet interface on the
RZ/G3L SMARC SoM board and also enable hotplug support.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430125342.439755-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index acead2b1c842b868658e13f97997a1e5885a0ec3..0ae052238b3b524e920fcc344ea97c9a4aa07c68 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -14,6 +14,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
 #include "r9a08g046l48.dtsi"
 #include "rzg3l-smarc-som.dtsi"
 #include "renesas-smarc2.dtsi"

diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index fb781d9035aa6dafe979a689ddb2f55734e55553..c7227a865fa407b421ec45435c49c5c2ba013137 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -23,6 +23,8 @@
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
 
+       pinctrl-0 = <&eth0_pins>;
+       pinctrl-names = "default";
        status = "okay";
 };
 
@@ -38,6 +40,7 @@
        phy0: ethernet-phy@7 {
                compatible = "ethernet-phy-id0022.1640";
                reg = <7>;
+               interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
                rxc-skew-psec = <1400>;
                txc-skew-psec = <1400>;
                rxdv-skew-psec = <0>;
@@ -52,3 +55,32 @@
                txd3-skew-psec = <0>;
        };
 };
+
+&pinctrl {
+       eth0_pins: eth0 {
+               txc {
+                       pinmux = <RZG3L_PORT_PINMUX(B, 1, 1)>;  /* ETH0_TXC_REF_CLK */
+                       power-source = <1800>;
+                       output-enable;
+                       drive-strength-microamp = <5200>;
+               };
+
+               ctrl {
+                       pinmux = <RZG3L_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+                                <RZG3L_PORT_PINMUX(A, 1, 1)>, /* MDC */
+                                <RZG3L_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+                                <RZG3L_PORT_PINMUX(A, 3, 1)>, /* TX_CTL */
+                                <RZG3L_PORT_PINMUX(B, 0, 1)>, /* RXC */
+                                <RZG3L_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+                                <RZG3L_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+                                <RZG3L_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+                                <RZG3L_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+                                <RZG3L_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+                                <RZG3L_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+                                <RZG3L_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+                                <RZG3L_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+                                <RZG3L_PORT_PINMUX(C, 2, 15)>; /* PHY_INTR */
+                                power-source = <1800>;
+               };
+       };
+};