drm/radeon/kms: DCE6.1 disp eng pll updates

DCE6.1 uses EXT_PLL1 for disp eng.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 6fe4a6dc4d6e345f7aaedfdc873ecdc11fa54032..224775beb478d121a530b57afe3de7f504bf81bf 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -767,7 +767,9 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
                         * SetPixelClock provides the dividers
                         */
                        args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
-                       if (ASIC_IS_DCE6(rdev))
+                       if (ASIC_IS_DCE61(rdev))
+                               args.v6.ucPpll = ATOM_EXT_PLL1;
+                       else if (ASIC_IS_DCE6(rdev))
                                args.v6.ucPpll = ATOM_PPLL0;
                        else
                                args.v6.ucPpll = ATOM_DCPLL;