--- /dev/null
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static void _test_drintx(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintn(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+static void _test_diex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diex %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxex %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpo(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpo 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpo 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpo 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpo 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpo 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpo 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpo 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpo 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpu(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpu 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpu 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpu 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpu 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpu 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpu 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpu 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpu 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+// Quad instruction testing
+static void _test_drintxq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintnq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_diexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diexq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxexq %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpoq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF );
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpoq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpoq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpoq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpoq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpoq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpoq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpoq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpoq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpuq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpuq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpuq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpuq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpuq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpuq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpuq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpuq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpuq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrnd(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 31) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrndq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%dn", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dqua(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static int TE_vals[] = { -16, -2, 0, 5};
+#define TE_VAL_LEN sizeof(TE_vals)/sizeof(int)
+static Bool __is_TE_val(int x)
+{
+ int i;
+ for (i = 0; i < TE_VAL_LEN; i++) {
+ if (x==TE_vals[i])
+ return True;
+ }
+ return False;
+}
+
+static void _test_dquai(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaiq(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+typedef void (*test_func_t)(int a, int b);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length.
+// If that length is changed, t
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+static dfp_one_arg_test_t
+dfp_quai_tests[] = {
+ { &_test_dquai, "dquai", LONG_TEST, "[QI]"},
+ { &_test_dquaiq, "dquaiq", QUAD_TEST, "[QI]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_quai_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_quai_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_quai_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int TE, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (TE = 0; TE < TE_VAL_LEN; TE++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(TE_vals[TE], RMC);
+ res = f18;
+ printf("%s (RMC=%2d, TE=%3d) %s %016llx", test_def.name, RMC,
+ TE_vals[TE], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_qua_tests[] = {
+ { &_test_dqua, "dqua", dfp_2args_x1, 25, LONG_TEST, "[Q]"},
+ { &_test_dquaq, "dquaq", dfp_2args_x1, 25, QUAD_TEST, "[Q]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_qua_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0, BF;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_qua_tests[k].test_func)) {
+ int i, RMC;
+ dfp_test_t test_def = dfp_qua_tests[k];
+ BF = 0;
+
+ for (i = 0; i < test_def.num_tests; i++) {
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%2d) %s %016llx", test_def.name, RMC, test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(", %016llx => %016llx\n", u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx, %016llx %016llx ==> %016llx %016llx\n",u0x, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_rrnd_tests[] = {
+ { &_test_drrnd, "drrnd", LONG_TEST, "[RR]"},
+ { &_test_drrndq, "drrndq", QUAD_TEST, "[RR]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rrnd_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, reference_sig, *reference_sig_p;
+ long long reference_sig_vals[] = {0ULL, 2ULL, 6ULL, 63ULL};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(long long);
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ reference_sig_p = &reference_sig;
+
+ while ((func = dfp_rrnd_tests[k].test_func)) {
+ int i, j;
+ dfp_one_arg_test_t test_def = dfp_rrnd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int R, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ *(long long *)reference_sig_p = reference_sig_vals[j];
+ f14 = reference_sig;
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%d, ref sig=%d) %s%016llx", test_def.name, RMC,
+ (int)reference_sig_vals[j], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_xiex_tests[] = {
+ { &_test_diex, "diex", LONG_TEST, ">>"},
+ { &_test_diexq, "diexq", QUAD_TEST, ">>"},
+ { &_test_dxex, "dxex", LONG_TEST, "<<"},
+ { &_test_dxexq, "dxexq", QUAD_TEST, "<<"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_xiex_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, target_exp, *target_exp_p;
+ /* The first two positions are placeholders and will be filled in later,
+ * based on the precision of the DFP argument.
+ */
+ long long target_exp_vals[] = {0ULL, 0ULL, 0ULL, -1ULL, -2ULL, -3ULL, -4ULL, -5ULL};
+ int num_exp_vals = sizeof(target_exp_vals)/sizeof(long long);
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ target_exp_p = &target_exp;
+
+ while ((func = dfp_xiex_tests[k].test_func)) {
+ int i;
+ Bool insert_insn = False;
+ dfp_one_arg_test_t test_def = dfp_xiex_tests[k];
+
+ if (!strncmp(test_def.name, "di", 2))
+ insert_insn = True;
+
+ if (test_def.precision == QUAD_TEST) {
+ target_exp_vals[0] = 12288ULL; // > max biased exponent
+ target_exp_vals[1] = 5235ULL;
+ } else {
+ target_exp_vals[0] = 768ULL; // > max biased exponent
+ target_exp_vals[1] = 355ULL;
+ }
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int j;
+
+ if (test_def.precision == QUAD_TEST) {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ } else {
+ u0 = dfp64_vals[i];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ if (!insert_insn) {
+ // This is just for extract insns (dexex[q])
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s ", test_def.name, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ continue;
+ }
+ // The following for-loop is just for insert insns (diex[q])
+ for (j = 0; j < num_exp_vals; j++) {
+ *(long long *)target_exp_p = target_exp_vals[j];
+ f14 = target_exp;
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s %5d, ", test_def.name, test_def.op, (int)target_exp_vals[j]);
+
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_test_t
+dfp_rint_tests[] = {
+ { &_test_drintn, "drintn", LONG_TEST, "~"},
+ { &_test_drintnq, "drintnq", QUAD_TEST, "~"},
+ { &_test_drintx, "drintx", LONG_TEST, "~"},
+ { &_test_drintxq, "drintxq", QUAD_TEST, "~"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rint_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_rint_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_rint_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int R, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (R = 0; R < 2; R++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(R, RMC);
+ res = f18;
+ printf("%s (RM=%d) %s%016llx", test_def.name, (RMC + (R << 2)), test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_test_t
+dfp_cmp_tests[] = {
+ { &_test_dcmpo, "dcmpo", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpoq, "dcmpoq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { &_test_dcmpu, "dcmpu", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpuq, "dcmpuq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_cmp_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the compare should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int k = 0, BF;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_cmp_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_def = dfp_cmp_tests[k];
+ BF = 0;
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx => %x (BF=%d)\n",
+ test_def.op, u1, condreg, BF);
+ } else {
+ printf(" %016llx %s %016llx %016llx ==> %x (BF=%d)\n",
+ u0x, test_def.op, u1, u1x,
+ condreg, BF);
+ }
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 5;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_cmp_ops,
+ "Test DFP compare instructions"},
+ { &test_dfp_rint_ops,
+ "Test DFP round instructions"},
+ { &test_dfp_xiex_ops,
+ "Test DFP insert/extract instructions"},
+ { &test_dfp_rrnd_ops,
+ "Test DFP reround instructions"},
+ { &test_dfp_qua_ops,
+ "Test DFP quantize instructions"},
+ { &test_dfp_quai_ops,
+ "Test DFP quantize immediate instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
--- /dev/null
+Test DFP compare instructions
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+Test DFP round instructions
+drintn (RM=0) ~2234000000000e50 => 22380000000001c5
+drintn (RM=1) ~2234000000000e50 => 22380000000001c5
+drintn (RM=2) ~2234000000000e50 => 22380000000001c5
+drintn (RM=3) ~2234000000000e50 => 22380000000001c5
+drintn (RM=4) ~2234000000000e50 => 22380000000001c5
+drintn (RM=5) ~2234000000000e50 => 22380000000001c5
+drintn (RM=6) ~2234000000000e50 => 22380000000001c5
+drintn (RM=7) ~2234000000000e50 => 22380000000001c5
+drintn (RM=0) ~223400000014c000 => 2238000000028c00
+drintn (RM=1) ~223400000014c000 => 2238000000028c00
+drintn (RM=2) ~223400000014c000 => 2238000000028c00
+drintn (RM=3) ~223400000014c000 => 2238000000028c00
+drintn (RM=4) ~223400000014c000 => 2238000000028c00
+drintn (RM=5) ~223400000014c000 => 2238000000028c00
+drintn (RM=6) ~223400000014c000 => 2238000000028c00
+drintn (RM=7) ~223400000014c000 => 2238000000028c00
+drintn (RM=0) ~a2340000000000e0 => a238000000000016
+drintn (RM=1) ~a2340000000000e0 => a238000000000016
+drintn (RM=2) ~a2340000000000e0 => a238000000000016
+drintn (RM=3) ~a2340000000000e0 => a238000000000016
+drintn (RM=4) ~a2340000000000e0 => a238000000000016
+drintn (RM=5) ~a2340000000000e0 => a238000000000016
+drintn (RM=6) ~a2340000000000e0 => a238000000000016
+drintn (RM=7) ~a2340000000000e0 => a238000000000016
+drintn (RM=0) ~22240000000000cf => 2238000000000000
+drintn (RM=1) ~22240000000000cf => 2238000000000000
+drintn (RM=2) ~22240000000000cf => 2238000000000000
+drintn (RM=3) ~22240000000000cf => 2238000000000000
+drintn (RM=4) ~22240000000000cf => 2238000000000001
+drintn (RM=5) ~22240000000000cf => 2238000000000000
+drintn (RM=6) ~22240000000000cf => 2238000000000001
+drintn (RM=7) ~22240000000000cf => 2238000000000000
+drintn (RM=0) ~a21400010a395bcf => a238000000000004
+drintn (RM=1) ~a21400010a395bcf => a238000000000004
+drintn (RM=2) ~a21400010a395bcf => a238000000000004
+drintn (RM=3) ~a21400010a395bcf => a238000000000004
+drintn (RM=4) ~a21400010a395bcf => a238000000000004
+drintn (RM=5) ~a21400010a395bcf => a238000000000005
+drintn (RM=6) ~a21400010a395bcf => a238000000000005
+drintn (RM=7) ~a21400010a395bcf => a238000000000004
+drintn (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=0) ~000400000089b000 => 2238000000000000
+drintn (RM=1) ~000400000089b000 => 2238000000000000
+drintn (RM=2) ~000400000089b000 => 2238000000000000
+drintn (RM=3) ~000400000089b000 => 2238000000000000
+drintn (RM=4) ~000400000089b000 => 2238000000000001
+drintn (RM=5) ~000400000089b000 => 2238000000000000
+drintn (RM=6) ~000400000089b000 => 2238000000000001
+drintn (RM=7) ~000400000089b000 => 2238000000000000
+drintn (RM=0) ~2238000000000000 => 2238000000000000
+drintn (RM=1) ~2238000000000000 => 2238000000000000
+drintn (RM=2) ~2238000000000000 => 2238000000000000
+drintn (RM=3) ~2238000000000000 => 2238000000000000
+drintn (RM=4) ~2238000000000000 => 2238000000000000
+drintn (RM=5) ~2238000000000000 => 2238000000000000
+drintn (RM=6) ~2238000000000000 => 2238000000000000
+drintn (RM=7) ~2238000000000000 => 2238000000000000
+drintn (RM=0) ~a238000000000000 => a238000000000000
+drintn (RM=1) ~a238000000000000 => a238000000000000
+drintn (RM=2) ~a238000000000000 => a238000000000000
+drintn (RM=3) ~a238000000000000 => a238000000000000
+drintn (RM=4) ~a238000000000000 => a238000000000000
+drintn (RM=5) ~a238000000000000 => a238000000000000
+drintn (RM=6) ~a238000000000000 => a238000000000000
+drintn (RM=7) ~a238000000000000 => a238000000000000
+drintn (RM=0) ~4248000000000000 => 4248000000000000
+drintn (RM=1) ~4248000000000000 => 4248000000000000
+drintn (RM=2) ~4248000000000000 => 4248000000000000
+drintn (RM=3) ~4248000000000000 => 4248000000000000
+drintn (RM=4) ~4248000000000000 => 4248000000000000
+drintn (RM=5) ~4248000000000000 => 4248000000000000
+drintn (RM=6) ~4248000000000000 => 4248000000000000
+drintn (RM=7) ~4248000000000000 => 4248000000000000
+drintn (RM=0) ~7e34000000000111 => 7c00000000000111
+drintn (RM=1) ~7e34000000000111 => 7c00000000000111
+drintn (RM=2) ~7e34000000000111 => 7c00000000000111
+drintn (RM=3) ~7e34000000000111 => 7c00000000000111
+drintn (RM=4) ~7e34000000000111 => 7c00000000000111
+drintn (RM=5) ~7e34000000000111 => 7c00000000000111
+drintn (RM=6) ~7e34000000000111 => 7c00000000000111
+drintn (RM=7) ~7e34000000000111 => 7c00000000000111
+drintn (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=0) ~fc00000000000000 => fc00000000000000
+drintn (RM=1) ~fc00000000000000 => fc00000000000000
+drintn (RM=2) ~fc00000000000000 => fc00000000000000
+drintn (RM=3) ~fc00000000000000 => fc00000000000000
+drintn (RM=4) ~fc00000000000000 => fc00000000000000
+drintn (RM=5) ~fc00000000000000 => fc00000000000000
+drintn (RM=6) ~fc00000000000000 => fc00000000000000
+drintn (RM=7) ~fc00000000000000 => fc00000000000000
+drintn (RM=0) ~7800000000000000 => 7800000000000000
+drintn (RM=1) ~7800000000000000 => 7800000000000000
+drintn (RM=2) ~7800000000000000 => 7800000000000000
+drintn (RM=3) ~7800000000000000 => 7800000000000000
+drintn (RM=4) ~7800000000000000 => 7800000000000000
+drintn (RM=5) ~7800000000000000 => 7800000000000000
+drintn (RM=6) ~7800000000000000 => 7800000000000000
+drintn (RM=7) ~7800000000000000 => 7800000000000000
+drintn (RM=0) ~f800000000000000 => f800000000000000
+drintn (RM=1) ~f800000000000000 => f800000000000000
+drintn (RM=2) ~f800000000000000 => f800000000000000
+drintn (RM=3) ~f800000000000000 => f800000000000000
+drintn (RM=4) ~f800000000000000 => f800000000000000
+drintn (RM=5) ~f800000000000000 => f800000000000000
+drintn (RM=6) ~f800000000000000 => f800000000000000
+drintn (RM=7) ~f800000000000000 => f800000000000000
+drintn (RM=0) ~7a34000000000000 => 7800000000000000
+drintn (RM=1) ~7a34000000000000 => 7800000000000000
+drintn (RM=2) ~7a34000000000000 => 7800000000000000
+drintn (RM=3) ~7a34000000000000 => 7800000000000000
+drintn (RM=4) ~7a34000000000000 => 7800000000000000
+drintn (RM=5) ~7a34000000000000 => 7800000000000000
+drintn (RM=6) ~7a34000000000000 => 7800000000000000
+drintn (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintnq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+drintx (RM=0) ~2234000000000e50 => 22380000000001c5
+drintx (RM=1) ~2234000000000e50 => 22380000000001c5
+drintx (RM=2) ~2234000000000e50 => 22380000000001c5
+drintx (RM=3) ~2234000000000e50 => 22380000000001c5
+drintx (RM=4) ~2234000000000e50 => 22380000000001c5
+drintx (RM=5) ~2234000000000e50 => 22380000000001c5
+drintx (RM=6) ~2234000000000e50 => 22380000000001c5
+drintx (RM=7) ~2234000000000e50 => 22380000000001c5
+drintx (RM=0) ~223400000014c000 => 2238000000028c00
+drintx (RM=1) ~223400000014c000 => 2238000000028c00
+drintx (RM=2) ~223400000014c000 => 2238000000028c00
+drintx (RM=3) ~223400000014c000 => 2238000000028c00
+drintx (RM=4) ~223400000014c000 => 2238000000028c00
+drintx (RM=5) ~223400000014c000 => 2238000000028c00
+drintx (RM=6) ~223400000014c000 => 2238000000028c00
+drintx (RM=7) ~223400000014c000 => 2238000000028c00
+drintx (RM=0) ~a2340000000000e0 => a238000000000016
+drintx (RM=1) ~a2340000000000e0 => a238000000000016
+drintx (RM=2) ~a2340000000000e0 => a238000000000016
+drintx (RM=3) ~a2340000000000e0 => a238000000000016
+drintx (RM=4) ~a2340000000000e0 => a238000000000016
+drintx (RM=5) ~a2340000000000e0 => a238000000000016
+drintx (RM=6) ~a2340000000000e0 => a238000000000016
+drintx (RM=7) ~a2340000000000e0 => a238000000000016
+drintx (RM=0) ~22240000000000cf => 2238000000000000
+drintx (RM=1) ~22240000000000cf => 2238000000000000
+drintx (RM=2) ~22240000000000cf => 2238000000000000
+drintx (RM=3) ~22240000000000cf => 2238000000000000
+drintx (RM=4) ~22240000000000cf => 2238000000000001
+drintx (RM=5) ~22240000000000cf => 2238000000000000
+drintx (RM=6) ~22240000000000cf => 2238000000000001
+drintx (RM=7) ~22240000000000cf => 2238000000000000
+drintx (RM=0) ~a21400010a395bcf => a238000000000004
+drintx (RM=1) ~a21400010a395bcf => a238000000000004
+drintx (RM=2) ~a21400010a395bcf => a238000000000004
+drintx (RM=3) ~a21400010a395bcf => a238000000000004
+drintx (RM=4) ~a21400010a395bcf => a238000000000004
+drintx (RM=5) ~a21400010a395bcf => a238000000000005
+drintx (RM=6) ~a21400010a395bcf => a238000000000005
+drintx (RM=7) ~a21400010a395bcf => a238000000000004
+drintx (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=0) ~000400000089b000 => 2238000000000000
+drintx (RM=1) ~000400000089b000 => 2238000000000000
+drintx (RM=2) ~000400000089b000 => 2238000000000000
+drintx (RM=3) ~000400000089b000 => 2238000000000000
+drintx (RM=4) ~000400000089b000 => 2238000000000001
+drintx (RM=5) ~000400000089b000 => 2238000000000000
+drintx (RM=6) ~000400000089b000 => 2238000000000001
+drintx (RM=7) ~000400000089b000 => 2238000000000000
+drintx (RM=0) ~2238000000000000 => 2238000000000000
+drintx (RM=1) ~2238000000000000 => 2238000000000000
+drintx (RM=2) ~2238000000000000 => 2238000000000000
+drintx (RM=3) ~2238000000000000 => 2238000000000000
+drintx (RM=4) ~2238000000000000 => 2238000000000000
+drintx (RM=5) ~2238000000000000 => 2238000000000000
+drintx (RM=6) ~2238000000000000 => 2238000000000000
+drintx (RM=7) ~2238000000000000 => 2238000000000000
+drintx (RM=0) ~a238000000000000 => a238000000000000
+drintx (RM=1) ~a238000000000000 => a238000000000000
+drintx (RM=2) ~a238000000000000 => a238000000000000
+drintx (RM=3) ~a238000000000000 => a238000000000000
+drintx (RM=4) ~a238000000000000 => a238000000000000
+drintx (RM=5) ~a238000000000000 => a238000000000000
+drintx (RM=6) ~a238000000000000 => a238000000000000
+drintx (RM=7) ~a238000000000000 => a238000000000000
+drintx (RM=0) ~4248000000000000 => 4248000000000000
+drintx (RM=1) ~4248000000000000 => 4248000000000000
+drintx (RM=2) ~4248000000000000 => 4248000000000000
+drintx (RM=3) ~4248000000000000 => 4248000000000000
+drintx (RM=4) ~4248000000000000 => 4248000000000000
+drintx (RM=5) ~4248000000000000 => 4248000000000000
+drintx (RM=6) ~4248000000000000 => 4248000000000000
+drintx (RM=7) ~4248000000000000 => 4248000000000000
+drintx (RM=0) ~7e34000000000111 => 7c00000000000111
+drintx (RM=1) ~7e34000000000111 => 7c00000000000111
+drintx (RM=2) ~7e34000000000111 => 7c00000000000111
+drintx (RM=3) ~7e34000000000111 => 7c00000000000111
+drintx (RM=4) ~7e34000000000111 => 7c00000000000111
+drintx (RM=5) ~7e34000000000111 => 7c00000000000111
+drintx (RM=6) ~7e34000000000111 => 7c00000000000111
+drintx (RM=7) ~7e34000000000111 => 7c00000000000111
+drintx (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=0) ~fc00000000000000 => fc00000000000000
+drintx (RM=1) ~fc00000000000000 => fc00000000000000
+drintx (RM=2) ~fc00000000000000 => fc00000000000000
+drintx (RM=3) ~fc00000000000000 => fc00000000000000
+drintx (RM=4) ~fc00000000000000 => fc00000000000000
+drintx (RM=5) ~fc00000000000000 => fc00000000000000
+drintx (RM=6) ~fc00000000000000 => fc00000000000000
+drintx (RM=7) ~fc00000000000000 => fc00000000000000
+drintx (RM=0) ~7800000000000000 => 7800000000000000
+drintx (RM=1) ~7800000000000000 => 7800000000000000
+drintx (RM=2) ~7800000000000000 => 7800000000000000
+drintx (RM=3) ~7800000000000000 => 7800000000000000
+drintx (RM=4) ~7800000000000000 => 7800000000000000
+drintx (RM=5) ~7800000000000000 => 7800000000000000
+drintx (RM=6) ~7800000000000000 => 7800000000000000
+drintx (RM=7) ~7800000000000000 => 7800000000000000
+drintx (RM=0) ~f800000000000000 => f800000000000000
+drintx (RM=1) ~f800000000000000 => f800000000000000
+drintx (RM=2) ~f800000000000000 => f800000000000000
+drintx (RM=3) ~f800000000000000 => f800000000000000
+drintx (RM=4) ~f800000000000000 => f800000000000000
+drintx (RM=5) ~f800000000000000 => f800000000000000
+drintx (RM=6) ~f800000000000000 => f800000000000000
+drintx (RM=7) ~f800000000000000 => f800000000000000
+drintx (RM=0) ~7a34000000000000 => 7800000000000000
+drintx (RM=1) ~7a34000000000000 => 7800000000000000
+drintx (RM=2) ~7a34000000000000 => 7800000000000000
+drintx (RM=3) ~7a34000000000000 => 7800000000000000
+drintx (RM=4) ~7a34000000000000 => 7800000000000000
+drintx (RM=5) ~7a34000000000000 => 7800000000000000
+drintx (RM=6) ~7a34000000000000 => 7800000000000000
+drintx (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintxq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP insert/extract instructions
+diex >> 768, 2234000000000e50 => 7c00000000000e50
+diex >> 355, 2234000000000e50 => 218c000000000e50
+diex >> 0, 2234000000000e50 => 0000000000000e50
+diex >> -1, 2234000000000e50 => 7800000000000e50
+diex >> -2, 2234000000000e50 => 7c00000000000e50
+diex >> -3, 2234000000000e50 => 7e00000000000e50
+diex >> -4, 2234000000000e50 => 7c00000000000e50
+diex >> -5, 2234000000000e50 => 7c00000000000e50
+diex >> 768, 223400000014c000 => 7c0000000014c000
+diex >> 355, 223400000014c000 => 218c00000014c000
+diex >> 0, 223400000014c000 => 000000000014c000
+diex >> -1, 223400000014c000 => 780000000014c000
+diex >> -2, 223400000014c000 => 7c0000000014c000
+diex >> -3, 223400000014c000 => 7e0000000014c000
+diex >> -4, 223400000014c000 => 7c0000000014c000
+diex >> -5, 223400000014c000 => 7c0000000014c000
+diex >> 768, a2340000000000e0 => fc000000000000e0
+diex >> 355, a2340000000000e0 => a18c0000000000e0
+diex >> 0, a2340000000000e0 => 80000000000000e0
+diex >> -1, a2340000000000e0 => f8000000000000e0
+diex >> -2, a2340000000000e0 => fc000000000000e0
+diex >> -3, a2340000000000e0 => fe000000000000e0
+diex >> -4, a2340000000000e0 => fc000000000000e0
+diex >> -5, a2340000000000e0 => fc000000000000e0
+diex >> 768, 22240000000000cf => 7c000000000000cf
+diex >> 355, 22240000000000cf => 218c0000000000cf
+diex >> 0, 22240000000000cf => 00000000000000cf
+diex >> -1, 22240000000000cf => 78000000000000cf
+diex >> -2, 22240000000000cf => 7c000000000000cf
+diex >> -3, 22240000000000cf => 7e000000000000cf
+diex >> -4, 22240000000000cf => 7c000000000000cf
+diex >> -5, 22240000000000cf => 7c000000000000cf
+diex >> 768, a21400010a395bcf => fc0000010a395bcf
+diex >> 355, a21400010a395bcf => a18c00010a395bcf
+diex >> 0, a21400010a395bcf => 800000010a395bcf
+diex >> -1, a21400010a395bcf => f80000010a395bcf
+diex >> -2, a21400010a395bcf => fc0000010a395bcf
+diex >> -3, a21400010a395bcf => fe0000010a395bcf
+diex >> -4, a21400010a395bcf => fc0000010a395bcf
+diex >> -5, a21400010a395bcf => fc0000010a395bcf
+diex >> 768, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 355, 6e4d3f1f534acdd4 => 6d8d3f1f534acdd4
+diex >> 0, 6e4d3f1f534acdd4 => 64013f1f534acdd4
+diex >> -1, 6e4d3f1f534acdd4 => 78013f1f534acdd4
+diex >> -2, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -3, 6e4d3f1f534acdd4 => 7e013f1f534acdd4
+diex >> -4, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -5, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 768, 000400000089b000 => 7c0000000089b000
+diex >> 355, 000400000089b000 => 218c00000089b000
+diex >> 0, 000400000089b000 => 000000000089b000
+diex >> -1, 000400000089b000 => 780000000089b000
+diex >> -2, 000400000089b000 => 7c0000000089b000
+diex >> -3, 000400000089b000 => 7e0000000089b000
+diex >> -4, 000400000089b000 => 7c0000000089b000
+diex >> -5, 000400000089b000 => 7c0000000089b000
+diex >> 768, 2238000000000000 => 7c00000000000000
+diex >> 355, 2238000000000000 => 218c000000000000
+diex >> 0, 2238000000000000 => 0000000000000000
+diex >> -1, 2238000000000000 => 7800000000000000
+diex >> -2, 2238000000000000 => 7c00000000000000
+diex >> -3, 2238000000000000 => 7e00000000000000
+diex >> -4, 2238000000000000 => 7c00000000000000
+diex >> -5, 2238000000000000 => 7c00000000000000
+diex >> 768, a238000000000000 => fc00000000000000
+diex >> 355, a238000000000000 => a18c000000000000
+diex >> 0, a238000000000000 => 8000000000000000
+diex >> -1, a238000000000000 => f800000000000000
+diex >> -2, a238000000000000 => fc00000000000000
+diex >> -3, a238000000000000 => fe00000000000000
+diex >> -4, a238000000000000 => fc00000000000000
+diex >> -5, a238000000000000 => fc00000000000000
+diex >> 768, 4248000000000000 => 7c00000000000000
+diex >> 355, 4248000000000000 => 218c000000000000
+diex >> 0, 4248000000000000 => 0000000000000000
+diex >> -1, 4248000000000000 => 7800000000000000
+diex >> -2, 4248000000000000 => 7c00000000000000
+diex >> -3, 4248000000000000 => 7e00000000000000
+diex >> -4, 4248000000000000 => 7c00000000000000
+diex >> -5, 4248000000000000 => 7c00000000000000
+diex >> 768, 7e34000000000111 => 7c00000000000111
+diex >> 355, 7e34000000000111 => 218c000000000111
+diex >> 0, 7e34000000000111 => 0000000000000111
+diex >> -1, 7e34000000000111 => 7800000000000111
+diex >> -2, 7e34000000000111 => 7c00000000000111
+diex >> -3, 7e34000000000111 => 7e00000000000111
+diex >> -4, 7e34000000000111 => 7c00000000000111
+diex >> -5, 7e34000000000111 => 7c00000000000111
+diex >> 768, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 355, fe000000d0e0a0d0 => a18c0000d0e0a0d0
+diex >> 0, fe000000d0e0a0d0 => 80000000d0e0a0d0
+diex >> -1, fe000000d0e0a0d0 => f8000000d0e0a0d0
+diex >> -2, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -3, fe000000d0e0a0d0 => fe000000d0e0a0d0
+diex >> -4, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -5, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 768, fc00000000000000 => fc00000000000000
+diex >> 355, fc00000000000000 => a18c000000000000
+diex >> 0, fc00000000000000 => 8000000000000000
+diex >> -1, fc00000000000000 => f800000000000000
+diex >> -2, fc00000000000000 => fc00000000000000
+diex >> -3, fc00000000000000 => fe00000000000000
+diex >> -4, fc00000000000000 => fc00000000000000
+diex >> -5, fc00000000000000 => fc00000000000000
+diex >> 768, 7800000000000000 => 7c00000000000000
+diex >> 355, 7800000000000000 => 218c000000000000
+diex >> 0, 7800000000000000 => 0000000000000000
+diex >> -1, 7800000000000000 => 7800000000000000
+diex >> -2, 7800000000000000 => 7c00000000000000
+diex >> -3, 7800000000000000 => 7e00000000000000
+diex >> -4, 7800000000000000 => 7c00000000000000
+diex >> -5, 7800000000000000 => 7c00000000000000
+diex >> 768, f800000000000000 => fc00000000000000
+diex >> 355, f800000000000000 => a18c000000000000
+diex >> 0, f800000000000000 => 8000000000000000
+diex >> -1, f800000000000000 => f800000000000000
+diex >> -2, f800000000000000 => fc00000000000000
+diex >> -3, f800000000000000 => fe00000000000000
+diex >> -4, f800000000000000 => fc00000000000000
+diex >> -5, f800000000000000 => fc00000000000000
+diex >> 768, 7a34000000000000 => 7c00000000000000
+diex >> 355, 7a34000000000000 => 218c000000000000
+diex >> 0, 7a34000000000000 => 0000000000000000
+diex >> -1, 7a34000000000000 => 7800000000000000
+diex >> -2, 7a34000000000000 => 7c00000000000000
+diex >> -3, 7a34000000000000 => 7e00000000000000
+diex >> -4, 7a34000000000000 => 7c00000000000000
+diex >> -5, 7a34000000000000 => 7c00000000000000
+
+diexq >> 12288, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 5235, 2207c00000000000 0000000000000e50 ==> 211cc00000000000 0000000000000e50
+diexq >> 0, 2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000000e50
+diexq >> -1, 2207c00000000000 0000000000000e50 ==> 7800000000000000 0000000000000e50
+diexq >> -2, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -3, 2207c00000000000 0000000000000e50 ==> 7e00000000000000 0000000000000e50
+diexq >> -4, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -5, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 12288, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 5235, 2207c00000000000 000000000014c000 ==> 211cc00000000000 000000000014c000
+diexq >> 0, 2207c00000000000 000000000014c000 ==> 0000000000000000 000000000014c000
+diexq >> -1, 2207c00000000000 000000000014c000 ==> 7800000000000000 000000000014c000
+diexq >> -2, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -3, 2207c00000000000 000000000014c000 ==> 7e00000000000000 000000000014c000
+diexq >> -4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -5, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 12288, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 5235, a207c00000000000 00000000000000e0 ==> a11cc00000000000 00000000000000e0
+diexq >> 0, a207c00000000000 00000000000000e0 ==> 8000000000000000 00000000000000e0
+diexq >> -1, a207c00000000000 00000000000000e0 ==> f800000000000000 00000000000000e0
+diexq >> -2, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -3, a207c00000000000 00000000000000e0 ==> fe00000000000000 00000000000000e0
+diexq >> -4, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -5, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 12288, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 5235, 2206c00000000000 00000000000000cf ==> 211cc00000000000 00000000000000cf
+diexq >> 0, 2206c00000000000 00000000000000cf ==> 0000000000000000 00000000000000cf
+diexq >> -1, 2206c00000000000 00000000000000cf ==> 7800000000000000 00000000000000cf
+diexq >> -2, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -3, 2206c00000000000 00000000000000cf ==> 7e00000000000000 00000000000000cf
+diexq >> -4, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -5, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 12288, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 5235, a205c00000000000 000000010a395bcf ==> a11cc00000000000 000000010a395bcf
+diexq >> 0, a205c00000000000 000000010a395bcf ==> 8000000000000000 000000010a395bcf
+diexq >> -1, a205c00000000000 000000010a395bcf ==> f800000000000000 000000010a395bcf
+diexq >> -2, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -3, a205c00000000000 000000010a395bcf ==> fe00000000000000 000000010a395bcf
+diexq >> -4, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -5, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 12288, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 5235, 6209400000fd0000 00253f1f534acdd4 ==> 691cc00000fd0000 00253f1f534acdd4
+diexq >> 0, 6209400000fd0000 00253f1f534acdd4 ==> 6000000000fd0000 00253f1f534acdd4
+diexq >> -1, 6209400000fd0000 00253f1f534acdd4 ==> 7800000000fd0000 00253f1f534acdd4
+diexq >> -2, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -3, 6209400000fd0000 00253f1f534acdd4 ==> 7e00000000fd0000 00253f1f534acdd4
+diexq >> -4, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -5, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 12288, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 5235, 000400000089b000 0a6000d000000049 ==> 211cc0000089b000 0a6000d000000049
+diexq >> 0, 000400000089b000 0a6000d000000049 ==> 000000000089b000 0a6000d000000049
+diexq >> -1, 000400000089b000 0a6000d000000049 ==> 780000000089b000 0a6000d000000049
+diexq >> -2, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -3, 000400000089b000 0a6000d000000049 ==> 7e0000000089b000 0a6000d000000049
+diexq >> -4, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -5, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 12288, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 2208000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 2208000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 2208000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a208000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a208000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a208000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a208000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a248000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a248000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a248000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a248000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7c00000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7c00000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7c00000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 5235, fc00000000000000 c00100035b007700 ==> a11cc00000000000 c00100035b007700
+diexq >> 0, fc00000000000000 c00100035b007700 ==> 8000000000000000 c00100035b007700
+diexq >> -1, fc00000000000000 c00100035b007700 ==> f800000000000000 c00100035b007700
+diexq >> -2, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -3, fc00000000000000 c00100035b007700 ==> fe00000000000000 c00100035b007700
+diexq >> -4, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -5, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 12288, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 5235, 7e00000000000000 fe000000d0e0a0d0 ==> 211cc00000000000 fe000000d0e0a0d0
+diexq >> 0, 7e00000000000000 fe000000d0e0a0d0 ==> 0000000000000000 fe000000d0e0a0d0
+diexq >> -1, 7e00000000000000 fe000000d0e0a0d0 ==> 7800000000000000 fe000000d0e0a0d0
+diexq >> -2, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -3, 7e00000000000000 fe000000d0e0a0d0 ==> 7e00000000000000 fe000000d0e0a0d0
+diexq >> -4, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -5, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 12288, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7800000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7800000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f800000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f800000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f800000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f900000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f900000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f900000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+
+dxex << 2234000000000e50 => 000000000000018d
+dxex << 223400000014c000 => 000000000000018d
+dxex << a2340000000000e0 => 000000000000018d
+dxex << 22240000000000cf => 0000000000000189
+dxex << a21400010a395bcf => 0000000000000185
+dxex << 6e4d3f1f534acdd4 => 0000000000000193
+dxex << 000400000089b000 => 0000000000000001
+dxex << 2238000000000000 => 000000000000018e
+dxex << a238000000000000 => 000000000000018e
+dxex << 4248000000000000 => 0000000000000292
+dxex << 7e34000000000111 => fffffffffffffffd
+dxex << fe000000d0e0a0d0 => fffffffffffffffd
+dxex << fc00000000000000 => fffffffffffffffe
+dxex << 7800000000000000 => ffffffffffffffff
+dxex << f800000000000000 => ffffffffffffffff
+dxex << 7a34000000000000 => ffffffffffffffff
+
+dxexq << 2207c00000000000 0000000000000e50 ==> 000000000000181f 0000000000000000
+dxexq << 2207c00000000000 000000000014c000 ==> 000000000000181f 0000000000000000
+dxexq << a207c00000000000 00000000000000e0 ==> 000000000000181f 0000000000000000
+dxexq << 2206c00000000000 00000000000000cf ==> 000000000000181b 0000000000000000
+dxexq << a205c00000000000 000000010a395bcf ==> 0000000000001817 0000000000000000
+dxexq << 6209400000fd0000 00253f1f534acdd4 ==> 0000000000000825 0000000000000000
+dxexq << 000400000089b000 0a6000d000000049 ==> 0000000000000010 0000000000000000
+dxexq << 2208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a248000000000000 0000000000000000 ==> 0000000000001920 0000000000000000
+dxexq << 7c00000000000000 0000000000000000 ==> fffffffffffffffe 0000000000000000
+dxexq << fc00000000000000 c00100035b007700 ==> fffffffffffffffe 0000000000000000
+dxexq << 7e00000000000000 fe000000d0e0a0d0 ==> fffffffffffffffd 0000000000000000
+dxexq << 7800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f900000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+
+Test DFP reround instructions
+drrnd (RMC=0, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=1, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=2, ref sig=2) [RR]2234000000000e50 => 223c000000000035
+drrnd (RMC=3, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=0, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=1, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=2, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=3, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=0, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=1, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=2, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=3, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=0, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=1, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=2, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=3, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=0, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=1, ref sig=2) [RR]22240000000000cf => 2228000000000018
+drrnd (RMC=2, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=3, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=0, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=1, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=2, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=3, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=0, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=1, ref sig=6) [RR]a21400010a395bcf => a2240000000849c5
+drrnd (RMC=2, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=3, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=0, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=1, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=2, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=3, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=0, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=1, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=2, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=3, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=0, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=1, ref sig=2) [RR]000400000089b000 => 001800000000004e
+drrnd (RMC=2, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=3, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=0, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=1, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=2, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=3, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=0, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000035
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=1, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=2, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=3, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=0, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=1, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000018
+drrndq (RMC=2, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=3, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=0, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=1, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=2, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=3, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=0, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=1, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+drrndq (RMC=2, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=3, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=0, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=1, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=2, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=3, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=0, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=1, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=2, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=3, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=0, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=1, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000010
+drrndq (RMC=2, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=3, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=0, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=1, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=2, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=3, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=0, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize instructions
+dqua (RMC= 0) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 1) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c5
+dqua (RMC= 2) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 3) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 0) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 1) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 2) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 3) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 0) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 1) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 2) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 3) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 0) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 1) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 2) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 3) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 0) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 1) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 2) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 3) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 0) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 1) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 2) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 3) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 0) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 1) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 2) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 3) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 0) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 1) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 2) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 3) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 1) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+dquaq (RMC= 2) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 3) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize immediate instructions
+dquai (RMC= 0, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 1, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 2, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 3, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 0, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 1, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 2, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 3, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 0, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 1, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 2, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 3, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 0, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 1, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 2, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 3, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 0, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 1, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 2, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 3, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 0, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 1, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 2, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 3, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 0, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 1, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 2, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 3, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 0, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 1, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 2, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 3, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 0, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 1, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 2, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 3, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 0, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 1, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 2, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 3, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 0, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 1, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 2, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 3, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 0, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 1, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 2, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 3, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 0, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 1, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 2, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 3, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 0, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 1, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 2, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 3, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 0, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 0, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 1, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 2, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 3, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 0, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 1, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 2, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 3, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 0, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 1, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 2, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 3, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 0, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 1, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 2, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 3, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 0, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 1, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 2, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 3, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 0, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 1, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 2, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 3, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 0, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
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+
projects / thirdparty / valgrind.git / commitdiff
