ARM: dts: zynq: Enable PL clocks for Parallella

commit 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c upstream.

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 41afd9da6876329811454ae9bb466ef6aa27af5a..229140b6de648a6a44cfe932372faf6062bdbddb 100644 (file)
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
        };
 };
 
+&clkc {
+       fclk-enable = <0xf>;
+};
+
 &gem0 {
        status = "okay";
        phy-mode = "rgmii-id";