arm64: dts: renesas: rzg3s-smarc: Enable PCIe

The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe
support.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 6b0bb2c441af50d9ab413ea416a2a16d40494055..70af605168b07c51fe03b9925cb85957dbdab580 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -155,6 +155,12 @@
        status = "okay";
 };
 
+&pcie {
+       pinctrl-0 = <&pcie_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &phyrst {
        status = "okay";
 };
@@ -186,6 +192,11 @@
                line-name = "key-3-gpio-irq";
        };
 
+       pcie_pins: pcie {
+               pinmux = <RZG2L_PORT_PINMUX(13, 2, 2)>, /* PCIE_RST_OUT_B */
+                        <RZG2L_PORT_PINMUX(13, 3, 2)>; /* PCIE_CLKREQ_B */
+       };
+
        scif0_pins: scif0 {
                pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
                         <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */