octeon_ep: disable per ring interrupts

Disable the MSI-X per ring interrupt for every PF ring when PF
netdev goes down.

Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs")
Signed-off-by: Sathesh Edara <sedara@marvell.com>
Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
Signed-off-by: Vimlesh Kumar <vimleshk@marvell.com>
Link: https://patch.msgid.link/20260206111510.1045092-2-vimleshk@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
index b5805969404fa14c9f923250190a97335b60ff62..f0bcb5f3c1474171f049364d0eeb3802e5783af4 100644 (file)
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
@@ -696,14 +696,26 @@ static void octep_enable_interrupts_cn93_pf(struct octep_device *oct)
 /* Disable all interrupts */
 static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)
 {
-       u64 intr_mask = 0ULL;
+       u64 reg_val, intr_mask = 0ULL;
        int srn, num_rings, i;
 
        srn = CFG_GET_PORTS_PF_SRN(oct->conf);
        num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
 
-       for (i = 0; i < num_rings; i++)
-               intr_mask |= (0x1ULL << (srn + i));
+       for (i = 0; i < num_rings; i++) {
+               intr_mask |= BIT_ULL(srn + i);
+               reg_val = octep_read_csr64(oct,
+                                          CN93_SDP_R_IN_INT_LEVELS(srn + i));
+               reg_val &= ~CN93_INT_ENA_BIT;
+               octep_write_csr64(oct,
+                                 CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val);
+
+               reg_val = octep_read_csr64(oct,
+                                          CN93_SDP_R_OUT_INT_LEVELS(srn + i));
+               reg_val &= ~CN93_INT_ENA_BIT;
+               octep_write_csr64(oct,
+                                 CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);
+       }
 
        octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);
        octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
index 5de0b5ecbc5fd13ba5e4a66a28a8edd84387c270..07e00887c6940a349f811724abdb837dbc78f92b 100644 (file)
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
@@ -720,14 +720,26 @@ static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct)
 /* Disable all interrupts */
 static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct)
 {
-       u64 intr_mask = 0ULL;
+       u64 reg_val, intr_mask = 0ULL;
        int srn, num_rings, i;
 
        srn = CFG_GET_PORTS_PF_SRN(oct->conf);
        num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
 
-       for (i = 0; i < num_rings; i++)
-               intr_mask |= (0x1ULL << (srn + i));
+       for (i = 0; i < num_rings; i++) {
+               intr_mask |= BIT_ULL(srn + i);
+               reg_val = octep_read_csr64(oct,
+                                          CNXK_SDP_R_IN_INT_LEVELS(srn + i));
+               reg_val &= ~CNXK_INT_ENA_BIT;
+               octep_write_csr64(oct,
+                                 CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val);
+
+               reg_val = octep_read_csr64(oct,
+                                          CNXK_SDP_R_OUT_INT_LEVELS(srn + i));
+               reg_val &= ~CNXK_INT_ENA_BIT;
+               octep_write_csr64(oct,
+                                 CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);
+       }
 
        octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);
        octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
index ca473502d7a02a36db082425ac7b8414ad91db2d..95f1dfff90cce475aa92954edbc9a4832a05958c 100644 (file)
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
@@ -386,5 +386,6 @@
 #define CN93_PEM_BAR4_INDEX            7
 #define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL
 #define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)
+#define CN93_INT_ENA_BIT       BIT_ULL(62)
 
 #endif /* _OCTEP_REGS_CN9K_PF_H_ */

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
index e637d7c8224d4967d9d2fba69c0d95bc88455358..4d172a552f80c5547d4d1c560743294107512564 100644 (file)
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
@@ -412,5 +412,6 @@
 #define CNXK_PEM_BAR4_INDEX            7
 #define CNXK_PEM_BAR4_INDEX_SIZE       0x400000ULL
 #define CNXK_PEM_BAR4_INDEX_OFFSET     (CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_INDEX_SIZE)
+#define CNXK_INT_ENA_BIT       BIT_ULL(62)
 
 #endif /* _OCTEP_REGS_CNXK_PF_H_ */