RISC-V: Add test for vec_duplicate + vmsne.vv combine case 1 with GR2VR cost 0, 1...

Add asm dump check and run test for vec_duplicate + vmsne.vv
combine to vmseq.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vmsne.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add the helper
	macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index d9cbe02d5fa9c2366e41aa21ef04710a132080a0..f3975be915b234c4eb1afb6dd2b1c6b6bd3d9a70 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 6c14e94a6bcc3fe55b5a5dd43caa18047008ac54..7d3e2af2ddd7b11bc16fbd3829a8fb957af62c91 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index c1d72169e25a325b4f5c68ccc4c27e7e1f2b1613..a581c027e039a4a3b9c38daedb2e0e5669c81f2c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */
 /* { dg-final { scan-assembler-times {vwmaccu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 87af77b33d4fc104608fae541a88083f44ff8351..65e98066b8e411939040239fafa05b92ddf373c0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 163bfc3b3fde3ae0b10ffb4bd5577bea7e2d22c1..f2beb3b2f119cf8c91327da70d9d553bffa6ae9d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index a04516e9bd051d371a500a6f9b644bf60c4fbc76..949210964f6098e260ac14c304f5c6430f71f7fa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 85962bf301392e7bf0e1416db4456e48477ae1b1..01027351b48b56c20acaa232e544e6f0a505b798 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 211def9f8e9c7b529ce8479bb03faff16a0fcaaf..5f0d75b5a97ce01ab8767ce324f6106425de24aa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 9f361967025980b42340c4b48f5d7c9d0a2a0ce8..8ac64b6a865050e305afcd0b8924c0c359bdce40 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 426d910e778f35d61a61f663e16927c8259fa484..cc126c2742707b11a635d6f3cc78a51ab90a256c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 755873007b670d4951924bedaa270eacb8145455..7642add8073d2f13b602dd914bc2bd5adc106ffb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -37,3 +37,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwsubu.wx} } } */
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index e8478495d2cf142319fab8a25387efedb2feccc3..c5f973024100471f3d86d772e796b9c33a2f9e6c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
+/* { dg-final { scan-assembler-not {vmsne.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 35805a33fcb7fce56bda160ad3dad649a1dbddd5..4a30de478650545a5a47a2c26e61a9d768a70f6c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -423,6 +423,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
   DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq)                            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne)                            \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)           \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index cb57660e6be1a294254685c8cd2d8059c3828e93..45976f7c4f4ac12db9448ba3a9fc92ac6fa0e98a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6294,4 +6294,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, eq)[][3][N] =
   },
 };
 
+uint8_t TEST_BINARY_DATA(uint8_t, ne)[][3][N] =
+{
+  {
+    { 127 },
+    {
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+      127, 127, 127, 127,
+      128, 128, 128, 128,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 255 },
+    {
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         2,   2,   2,   2,
+       255, 255, 255, 255,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, ne)[][3][N] =
+{
+  {
+    { 32767 },
+    {
+          0,     0,     0,     0,
+          1,     1,     1,     1,
+      32767, 32767, 32767, 32767,
+      32768, 32768, 32768, 32768,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 65535 },
+    {
+           0,     0,     0,     0,
+           1,     1,     1,     1,
+           2,     2,     2,     2,
+       65535, 65535, 65535, 65535,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, ne)[][3][N] =
+{
+  {
+    { 2147483647 },
+    {
+               0,          0,          0,          0,
+               1,          1,          1,          1,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      2147483648, 2147483648, 2147483648, 2147483648,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 4294967295 },
+    {
+                0,          0,          0,          0,
+                1,          1,          1,          1,
+                2,          2,          2,          2,
+       4294967295, 4294967295, 4294967295, 4294967295,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, ne)[][3][N] =
+{
+  {
+    { 9223372036854775807ull },
+    {
+                           0,                      0,                      0,                      0,
+                           1,                      1,                      1,                      1,
+      9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
+      9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 18446744073709551615ull },
+    {
+                             0,                       0,                       0,                       0,
+                             1,                       1,                       1,                       1,
+                             2,                       2,                       2,                       2,
+       18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u16.c
new file mode 100644 (file)
index 0000000..5976490
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME ne
+
+DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u32.c
new file mode 100644 (file)
index 0000000..c2fbe05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME ne
+
+DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u64.c
new file mode 100644 (file)
index 0000000..3431ed6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME ne
+
+DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u8.c
new file mode 100644 (file)
index 0000000..9ccebe5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsne-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME ne
+
+DEF_VX_BINARY_CASE_0_WRAP(T, !=, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"