]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ASoC: rockchip: spdif: Reorder clock enable sequence
authorbui duc phuc <phucduc.bui@gmail.com>
Tue, 2 Jun 2026 10:16:05 +0000 (17:16 +0700)
committerMark Brown <broonie@kernel.org>
Thu, 11 Jun 2026 19:49:39 +0000 (20:49 +0100)
Enable the 'hclk' bus clock before the 'mclk' controller clock during
runtime resume.
The bus clock provides the register access interface, so enable it before
the controller clock. This also makes the resume sequence the reverse of
the suspend sequence, which keeps the clock ordering consistent.

Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
Link: https://patch.msgid.link/20260602101608.45137-3-phucduc.bui@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/rockchip/rockchip_spdif.c

index 581624f2682ef3ca397fd7234a96dead7223e171..8de5b76cfe7916d3ba87bf868cfa325a3a16d50e 100644 (file)
@@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev)
        struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
        int ret;
 
-       ret = clk_prepare_enable(spdif->mclk);
+       ret = clk_prepare_enable(spdif->hclk);
        if (ret) {
-               dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
+               dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
                return ret;
        }
 
-       ret = clk_prepare_enable(spdif->hclk);
+       ret = clk_prepare_enable(spdif->mclk);
        if (ret) {
-               clk_disable_unprepare(spdif->mclk);
-               dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
+               clk_disable_unprepare(spdif->hclk);
+               dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
                return ret;
        }