RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0...

Add asm dump check and run test for vec_duplicate + vmacc.vvm
combine to vmacc.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index cb62e0f961997f5600eba99007606ed25f7069f4..187b681bea20e94b06610220c958f83422183fc2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint16_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index e2a5dbbc8599d20626a6609524273740016ae180..a3a785abf063990b3c97d17b2595ec53e23cd8b9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint32_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 8e7a78892613d900efe9df2675848beb596d244e..4142e1b67ec71e8dd860eb5801b6e8c63ff95417 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint64_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -23,3 +25,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
    } } } } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index d213c18d9aee1e735bb5aff0e19e820aa01815d5..5b36f084ac85e4acfaac191c3c52f16615d03a72 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint8_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 365e650ef12b293cd83b01fcd1271cd533550f5e..9c034dcf7c69ee73529d0aa19bf3ee17a55a3619 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint16_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index c8fd42a52c46a3e9f7c0d64341862202f6ec44d0..ce50de6919087a25d1950aa1f494745cf0db1110 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint32_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index bdb76b471c0c33731f34f2572a437a171b875c4a..5cd6b417092c5d4a58e415e34be3b3c73f6bad39 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint64_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index fc9c10125a8709e1bd7edb50ac6d4ed09e7700ef..f9d4a63198d0e1e7638cae23822cf1ba52845c38 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint8_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 121daebcf552e9c043c61fdd2de94dff957774d3..2264014e2e29304019a597f8c57e1ff9acbd8b09 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint16_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 9616e7f2fe45e3e4e430f22aadb43f004ce69fc5..928909386d9d569f08d663ccba164452bc60851c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint32_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index cf985f0ba269a3e94d4063f8f6423bd66338d82f..271b4d62e3f5c13fc9ef59603c7c1b703581027a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint64_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 3bb382dd395ef92351829bb770badb23573ae6a6..f75695b6b5cc5f31990ece54f4ecec3db2ac0f85 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T uint8_t
 
 TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vssubu.vx} } } */
 /* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
new file mode 100644 (file)
index 0000000..8ec9d05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint16_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
new file mode 100644 (file)
index 0000000..46d5c4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint32_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
new file mode 100644 (file)
index 0000000..cd857b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint64_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
new file mode 100644 (file)
index 0000000..05fa397
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint8_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"