iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits

HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE.
When kernel maps a clean but writable page, it will set PTE_READONLY and
PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU-
capable MMU will automatically clear the PTE_RDONLY bit without software
intervention.

On the other hand, SMMU has the same HTTU feature, yet it is not enabled
in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while
sharing the CPU page table, resulting in unnecessary stalls.

Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD.

Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index f1f8e01a7e9142a755395fdd09eafcf2e05256ba..1ed8a6f29dc4456493b3c7f86524155ec6a2e3a2 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -92,6 +92,16 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target,
 
                target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) &
                                              CTXDESC_CD_1_TTB0_MASK);
+
+               /*
+                * Enable Hardware Access and Dirty updates (DBM) if supported.
+                * This is safe to enable by default, as PTE_WRITE and PTE_DBM
+                * share the same bit.
+                */
+               if (master->smmu->features & ARM_SMMU_FEAT_HA)
+                       target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA);
+               if (master->smmu->features & ARM_SMMU_FEAT_HD)
+                       target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD);
        } else {
                target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_EPD0);