x86/resctrl: Fix memory bandwidth counter width for Hygon

The memory bandwidth calculation relies on reading the hardware counter
and measuring the delta between samples. To ensure accurate measurement,
the software reads the counter frequently enough to prevent it from
rolling over twice between reads.

The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits.
Hygon CPUs provide a 32-bit width counter, but they do not support the
MBM capability CPUID leaf (0xF.[ECX=1]:EAX) to report the width offset
(from 24 bits).

Consequently, the kernel falls back to the 24-bit default counter width,
which causes incorrect overflow handling on Hygon CPUs.

Fix this by explicitly setting the counter width offset to 8 bits (resulting
in a 32-bit total counter width) for Hygon CPUs.

Fixes: d8df126349da ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251209062650.1536952-3-shenxiaochen@open-hieco.net

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 10de1594d328f86749d7cb27b1bf7b6c0dc877a9..6ebff44a3f7544640bf05cd42121358132304d08 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -1021,8 +1021,19 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
                c->x86_cache_occ_scale = ebx;
                c->x86_cache_mbm_width_offset = eax & 0xff;
 
-               if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
-                       c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
+               if (!c->x86_cache_mbm_width_offset) {
+                       switch (c->x86_vendor) {
+                       case X86_VENDOR_AMD:
+                               c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
+                               break;
+                       case X86_VENDOR_HYGON:
+                               c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_HYGON;
+                               break;
+                       default:
+                               /* Leave c->x86_cache_mbm_width_offset as 0 */
+                               break;
+                       }
+               }
        }
 }
 

diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 4a916c84a322068906e66a953f7444b5f6ed7aa5..79c18657ede0a1e99c6ee7dddffa7cc5e584b34e 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -14,6 +14,9 @@
 
 #define MBM_CNTR_WIDTH_OFFSET_AMD      20
 
+/* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */
+#define MBM_CNTR_WIDTH_OFFSET_HYGON    8
+
 #define RMID_VAL_ERROR                 BIT_ULL(63)
 
 #define RMID_VAL_UNAVAIL               BIT_ULL(62)