drm/amd/display: Consider sink max slice width limitation for dsc

[ Upstream commit 6b34e7ed4ba583ee77032a4c850ff97ba16ad870 ]

[WHY&HOW]
The sink max slice width limitation should be considered for DSC, but
was removed in "refactor DSC cap calculations".
This patch adds it back and takes the valid minimum between the sink and
source.

Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 1f53a9f0c0ac30ae073cc862b80589013ab99698..e4144b2443324924ec698341e31c2e58056ec932 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1157,6 +1157,11 @@ static bool setup_dsc_config(
        if (!is_dsc_possible)
                goto done;
 
+       /* increase miniumum slice count to meet sink slice width limitations */
+       min_slices_h = dc_fixpt_ceil(dc_fixpt_max(
+                       dc_fixpt_div_int(dc_fixpt_from_int(pic_width), dsc_common_caps.max_slice_width), // sink min
+                       dc_fixpt_from_int(min_slices_h))); // source min
+
        min_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, min_slices_h);
 
        /* increase minimum slice count to meet sink throughput limitations */