]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
accel/amdxdna: Use a different name for latest firmware
authorLizhi Hou <lizhi.hou@amd.com>
Wed, 25 Feb 2026 20:47:52 +0000 (12:47 -0800)
committerLizhi Hou <lizhi.hou@amd.com>
Wed, 25 Feb 2026 21:51:31 +0000 (13:51 -0800)
Using legacy driver with latest firmware causes a power off issue.

Fix this by assigning a different filename (npu_7.sbin) to the latest
firmware. The driver attempts to load the latest firmware first and falls
back to the previous firmware version if loading fails.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5009
Fixes: f1eac46fe5f7 ("accel/amdxdna: Update firmware version check for latest firmware")
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20260225204752.2711734-1-lizhi.hou@amd.com
drivers/accel/amdxdna/aie2_pci.c
drivers/accel/amdxdna/amdxdna_pci_drv.c
drivers/accel/amdxdna/npu1_regs.c
drivers/accel/amdxdna/npu4_regs.c
drivers/accel/amdxdna/npu5_regs.c
drivers/accel/amdxdna/npu6_regs.c

index 4b3e6bb97bd2be934f830f1b01c99b4c1856785f..85079b6fc5d90a1cc0111043ba1f4e2f49b1bc75 100644 (file)
@@ -32,6 +32,11 @@ static int aie2_max_col = XRS_MAX_COL;
 module_param(aie2_max_col, uint, 0600);
 MODULE_PARM_DESC(aie2_max_col, "Maximum column could be used");
 
+static char *npu_fw[] = {
+       "npu_7.sbin",
+       "npu.sbin"
+};
+
 /*
  * The management mailbox channel is allocated by firmware.
  * The related register and ring buffer information is on SRAM BAR.
@@ -489,6 +494,7 @@ static int aie2_init(struct amdxdna_dev *xdna)
        struct psp_config psp_conf;
        const struct firmware *fw;
        unsigned long bars = 0;
+       char *fw_full_path;
        int i, nvec, ret;
 
        if (!hypervisor_is_type(X86_HYPER_NATIVE)) {
@@ -503,7 +509,19 @@ static int aie2_init(struct amdxdna_dev *xdna)
        ndev->priv = xdna->dev_info->dev_priv;
        ndev->xdna = xdna;
 
-       ret = request_firmware(&fw, ndev->priv->fw_path, &pdev->dev);
+       for (i = 0; i < ARRAY_SIZE(npu_fw); i++) {
+               fw_full_path = kasprintf(GFP_KERNEL, "%s%s", ndev->priv->fw_path, npu_fw[i]);
+               if (!fw_full_path)
+                       return -ENOMEM;
+
+               ret = firmware_request_nowarn(&fw, fw_full_path, &pdev->dev);
+               kfree(fw_full_path);
+               if (!ret) {
+                       XDNA_INFO(xdna, "Load firmware %s%s", ndev->priv->fw_path, npu_fw[i]);
+                       break;
+               }
+       }
+
        if (ret) {
                XDNA_ERR(xdna, "failed to request_firmware %s, ret %d",
                         ndev->priv->fw_path, ret);
index 4ada45d06fcf71aeaf13f45e30ad8bf4a0f716b8..a4384593bdccb6e50a227d8a3580825f1ae61d02 100644 (file)
@@ -23,6 +23,9 @@ MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");
 MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
 MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
 MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
+MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
 
 /*
  * 0.0: Initial version
index 6f36a27b5a02d88236eeb0407840d5af3314d0f5..6e3d3ca69c04ae588930f19c22febcb5a8967788 100644 (file)
@@ -72,7 +72,7 @@ static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
 };
 
 static const struct amdxdna_dev_priv npu1_dev_priv = {
-       .fw_path        = "amdnpu/1502_00/npu.sbin",
+       .fw_path        = "amdnpu/1502_00/",
        .rt_config      = npu1_default_rt_cfg,
        .dpm_clk_tbl    = npu1_dpm_clk_table,
        .fw_feature_tbl = npu1_fw_feature_table,
index a8d6f76dde5f9db21d966616cc23b68548749fd0..ce25eef5fc34f01df5e481b802bd9d054f4305c7 100644 (file)
@@ -98,7 +98,7 @@ const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = {
 };
 
 static const struct amdxdna_dev_priv npu4_dev_priv = {
-       .fw_path        = "amdnpu/17f0_10/npu.sbin",
+       .fw_path        = "amdnpu/17f0_10/",
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,
index c0a35cfd886cc44204f1c64c33953c263a45103a..c0ac5daf32ee5cbd58f17cf834b49164fc0355e0 100644 (file)
@@ -63,7 +63,7 @@
 #define NPU5_SRAM_BAR_BASE     MMNPU_APERTURE1_BASE
 
 static const struct amdxdna_dev_priv npu5_dev_priv = {
-       .fw_path        = "amdnpu/17f0_11/npu.sbin",
+       .fw_path        = "amdnpu/17f0_11/",
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,
index 1fb07df9918601535d11e6c72fdb87d3e343b452..ce591ed0d4832e39c27ed96baf496fc54d6700f0 100644 (file)
@@ -63,7 +63,7 @@
 #define NPU6_SRAM_BAR_BASE     MMNPU_APERTURE1_BASE
 
 static const struct amdxdna_dev_priv npu6_dev_priv = {
-       .fw_path        = "amdnpu/17f0_10/npu.sbin",
+       .fw_path        = "amdnpu/17f0_10/",
        .rt_config      = npu4_default_rt_cfg,
        .dpm_clk_tbl    = npu4_dpm_clk_table,
        .fw_feature_tbl = npu4_fw_feature_table,