module_param(aie2_max_col, uint, 0600);
MODULE_PARM_DESC(aie2_max_col, "Maximum column could be used");
+static char *npu_fw[] = {
+ "npu_7.sbin",
+ "npu.sbin"
+};
+
/*
* The management mailbox channel is allocated by firmware.
* The related register and ring buffer information is on SRAM BAR.
struct psp_config psp_conf;
const struct firmware *fw;
unsigned long bars = 0;
+ char *fw_full_path;
int i, nvec, ret;
if (!hypervisor_is_type(X86_HYPER_NATIVE)) {
ndev->priv = xdna->dev_info->dev_priv;
ndev->xdna = xdna;
- ret = request_firmware(&fw, ndev->priv->fw_path, &pdev->dev);
+ for (i = 0; i < ARRAY_SIZE(npu_fw); i++) {
+ fw_full_path = kasprintf(GFP_KERNEL, "%s%s", ndev->priv->fw_path, npu_fw[i]);
+ if (!fw_full_path)
+ return -ENOMEM;
+
+ ret = firmware_request_nowarn(&fw, fw_full_path, &pdev->dev);
+ kfree(fw_full_path);
+ if (!ret) {
+ XDNA_INFO(xdna, "Load firmware %s%s", ndev->priv->fw_path, npu_fw[i]);
+ break;
+ }
+ }
+
if (ret) {
XDNA_ERR(xdna, "failed to request_firmware %s, ret %d",
ndev->priv->fw_path, ret);
MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
+MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin");
+MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin");
/*
* 0.0: Initial version
};
static const struct amdxdna_dev_priv npu1_dev_priv = {
- .fw_path = "amdnpu/1502_00/npu.sbin",
+ .fw_path = "amdnpu/1502_00/",
.rt_config = npu1_default_rt_cfg,
.dpm_clk_tbl = npu1_dpm_clk_table,
.fw_feature_tbl = npu1_fw_feature_table,
};
static const struct amdxdna_dev_priv npu4_dev_priv = {
- .fw_path = "amdnpu/17f0_10/npu.sbin",
+ .fw_path = "amdnpu/17f0_10/",
.rt_config = npu4_default_rt_cfg,
.dpm_clk_tbl = npu4_dpm_clk_table,
.fw_feature_tbl = npu4_fw_feature_table,
#define NPU5_SRAM_BAR_BASE MMNPU_APERTURE1_BASE
static const struct amdxdna_dev_priv npu5_dev_priv = {
- .fw_path = "amdnpu/17f0_11/npu.sbin",
+ .fw_path = "amdnpu/17f0_11/",
.rt_config = npu4_default_rt_cfg,
.dpm_clk_tbl = npu4_dpm_clk_table,
.fw_feature_tbl = npu4_fw_feature_table,
#define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE
static const struct amdxdna_dev_priv npu6_dev_priv = {
- .fw_path = "amdnpu/17f0_10/npu.sbin",
+ .fw_path = "amdnpu/17f0_10/",
.rt_config = npu4_default_rt_cfg,
.dpm_clk_tbl = npu4_dpm_clk_table,
.fw_feature_tbl = npu4_fw_feature_table,