}
}
+static const MemoryRegionOps esdhc_mmio_be_ops = {
+ .read = esdhc_read,
+ .write = esdhc_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void fsl_esdhc_be_init(Object *obj)
+{
+ SDHCIState *s = SYSBUS_SDHCI(obj);
+ DeviceState *dev = DEVICE(obj);
+
+ s->io_ops = &esdhc_mmio_be_ops;
+ s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
+ qdev_prop_set_uint8(dev, "sd-spec-version", 2);
+ qdev_prop_set_uint8(dev, "vendor", SDHCI_VENDOR_FSL);
+}
+
static const MemoryRegionOps usdhc_mmio_ops = {
.read = esdhc_read,
.write = esdhc_write,
.instance_finalize = sdhci_sysbus_finalize,
.class_init = sdhci_sysbus_class_init,
},
+ {
+ .name = TYPE_FSL_ESDHC_BE,
+ .parent = TYPE_SYSBUS_SDHCI,
+ .instance_init = fsl_esdhc_be_init,
+ },
{
.name = TYPE_IMX_USDHC,
.parent = TYPE_SYSBUS_SDHCI,
DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI,
TYPE_SYSBUS_SDHCI)
+#define TYPE_FSL_ESDHC_BE "fsl-esdhc-be"
+
#define TYPE_IMX_USDHC "imx-usdhc"
#define TYPE_S3C_SDHCI "s3c-sdhci"