RISC-V: Fix splitter for 32-bit AND on 64-bit target.

Fixes github.com/riscv/riscv-gcc issue #161.  We were accidentally using
BITS_PER_WORD to compute shift counts when we should have been using the
bitsize of the operand modes.  This was wrong when we had an SImode shift
and a 64-bit target.

	Andrew Waterman  <andrew@sifive.com>
	gcc/
	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
	bitsize	instead of BITS_PER_WORD.
	gcc/testsuite/
	* gcc.target/riscv/shift-shift-2.c: Add one more test.

gcc/ChangeLog:
2019-07-18  Kito Cheng  <kito.cheng@sifive.com>

	Backport from mainline
	2019-07-08  Andrew Waterman  <andrew@sifive.com>
		    Jim Wilson  <jimw@sifive.com>

	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
	bitsize	instead of BITS_PER_WORD.
	gcc/testsuite/

gcc/testsuite/ChangeLog:
2019-07-18  Kito Cheng  <kito.cheng@sifive.com>

	Backport from mainline
	2019-07-08  Jim Wilson  <jimw@sifive.com>

	* gcc.target/riscv/shift-shift-2.c: Add one more test.

From-SVN: r273566

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6c61632e373b771e0bf810d509cac2ecfcbab69e..22716b0c0c0b8718b8e9a668589d92ca1e0d4d65 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2019-07-18  Kito Cheng  <kito.cheng@sifive.com>
+
+       Backport from mainline
+       2019-07-08  Andrew Waterman  <andrew@sifive.com>
+                   Jim Wilson  <jimw@sifive.com>
+
+       * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
+       bitsize instead of BITS_PER_WORD.
+       gcc/testsuite/
+
 2019-07-17  John David Anglin  <danglin@gcc.gnu.org>
 
        * config/pa/pa.c (pa_som_asm_init_sections): Don't force all constant

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e3799a5bdd8b6efed7ab457ac5ef9ed6fa35b393..a8bac170e72fd2d8d4134c9ad66fc23d2fe95b5c 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1775,10 +1775,11 @@
   (set (match_dup 0)
        (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
 {
-  operands[2] = GEN_INT (BITS_PER_WORD
+  /* Op2 is a VOIDmode constant, so get the mode size from op1.  */
+  operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1]))
                         - exact_log2 (INTVAL (operands[2]) + 1));
 })
-  
+
 ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros.  This can be
 ;; split into two shifts.  Otherwise it requires 3 instructions: li, sll, and.
 (define_split

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ecd4b6a71789258db7c25ba1dd8c0b9e79b077f2..de0b52ce248a59ddef850b4fa610745d2301683a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-18  Kito Cheng  <kito.cheng@sifive.com>
+
+       Backport from mainline
+       2019-07-08  Jim Wilson  <jimw@sifive.com>
+
+       * gcc.target/riscv/shift-shift-2.c: Add one more test.
+
 2019-07-17  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
index 3f07e7776e73ce53a68398b86cba35705077b434..10a5bb728bec22e5a7c28ac488dcc3ec58ee69a0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
@@ -25,5 +25,17 @@ sub4 (unsigned long i)
 {
   return (i << 52) >> 52;
 }
-/* { dg-final { scan-assembler-times "slli" 4 } } */
-/* { dg-final { scan-assembler-times "srli" 4 } } */
+
+unsigned int
+sub5 (unsigned int i)
+{
+  unsigned int j;
+  j = i >> 24;
+  j = j * (1 << 24);
+  j = i - j;
+  return j;
+}
+/* { dg-final { scan-assembler-times "slli" 5 } } */
+/* { dg-final { scan-assembler-times "srli" 5 } } */
+/* { dg-final { scan-assembler-times "slliw" 1 } } */
+/* { dg-final { scan-assembler-times "srliw" 1 } } */