drm/amd/pm: Workaround SI powertune issue on Radeon 430 (v2)

Radeon 430 and 520 are OEM GPUs from 2016~2017
They have the same device id: 0x6611 and revision: 0x87

On the Radeon 430, powertune is buggy and throttles the GPU,
never allowing it to reach its maximum SCLK. Work around this
bug by raising the TDP limits we program to the SMC from
24W (specified by the VBIOS on Radeon 430) to 32W.

Disabling powertune entirely is	not a viable workaround,
because	it causes the Radeon 520 to heat up above 100 C,
which I prefer to avoid.

Additionally, revise the maximum SCLK limit. Considering the
above issue, these GPUs never reached a high SCLK on Linux,
and the workarounds were added before the GPUs were released,
so the workaround likely didn't target these specifically.
Use 780 MHz (the maximum SCLK according to the VBIOS on the
Radeon 430). Note that the Radeon 520 VBIOS has a higher
maximum SCLK: 905 MHz, but in practice it doesn't seem to
perform better with the higher clock, only heats up more.

v2:
Move the workaround to si_populate_smc_tdp_limits.

Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 966d70f1e160bdfdecaf7ff2b3f22ad088516e9f)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 85f2b9540eabd65aa712d528c4333707cee52482..695432d3045ffae2302f5ba78a878abbe6248b8d 100644 (file)
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -2281,6 +2281,12 @@ static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
                if (ret)
                        return ret;
 
+               if (adev->pdev->device == 0x6611 && adev->pdev->revision == 0x87) {
+                       /* Workaround buggy powertune on Radeon 430 and 520. */
+                       tdp_limit = 32;
+                       near_tdp_limit = 28;
+               }
+
                smc_table->dpm2Params.TDPLimit =
                        cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
                smc_table->dpm2Params.NearTDPLimit =
@@ -3463,10 +3469,15 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
                    (adev->pdev->revision == 0x80) ||
                    (adev->pdev->revision == 0x81) ||
                    (adev->pdev->revision == 0x83) ||
-                   (adev->pdev->revision == 0x87) ||
+                   (adev->pdev->revision == 0x87 &&
+                               adev->pdev->device != 0x6611) ||
                    (adev->pdev->device == 0x6604) ||
                    (adev->pdev->device == 0x6605)) {
                        max_sclk = 75000;
+               } else if (adev->pdev->revision == 0x87 &&
+                               adev->pdev->device == 0x6611) {
+                       /* Radeon 430 and 520 */
+                       max_sclk = 78000;
                }
        }