ix86_attr_length_vex_default (rtx_insn *insn, bool has_0f_opcode,
bool has_vex_w)
{
- int i;
+ int i, reg_only = 2 + 1;
+ bool has_mem = false;
/* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
byte VEX prefix. */
if (GET_MODE (recog_data.operand[i]) == DImode
&& GENERAL_REG_P (recog_data.operand[i]))
return 3 + 1;
+
+ /* REX.B bit requires 3-byte VEX. Right here we don't know which
+ operand will be encoded using VEX.B, so be conservative. */
+ if (REX_INT_REGNO_P (recog_data.operand[i])
+ || REX_SSE_REGNO_P (recog_data.operand[i]))
+ reg_only = 3 + 1;
}
- else
+ else if (MEM_P (recog_data.operand[i]))
{
/* REX.X or REX.B bits use 3 byte VEX prefix. */
- if (MEM_P (recog_data.operand[i])
- && x86_extended_reg_mentioned_p (recog_data.operand[i]))
+ if (x86_extended_reg_mentioned_p (recog_data.operand[i]))
return 3 + 1;
+
+ has_mem = true;
}
- return 2 + 1;
+ return has_mem ? 2 + 1 : reg_only;
}
\f