]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
media: verisilicon: Enable NV15 support for Rockchip VDPU981
authorNicolas Dufresne <nicolas.dufresne@collabora.com>
Wed, 9 Apr 2025 19:30:09 +0000 (15:30 -0400)
committerHans Verkuil <hverkuil@xs4all.nl>
Thu, 24 Apr 2025 13:21:35 +0000 (15:21 +0200)
This is a "customer" format, though on Rockchip RK3588 it has been
verified to be NV15 format, which matches what the GPU and display
handles has 10bit pixel formats.

Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
drivers/media/platform/verisilicon/hantro_v4l2.c
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
drivers/media/platform/verisilicon/rockchip_vpu_hw.c

index 2bce940a58227c2bfef2bc3343992e4588ab36a4..7c3515cf7d64a090adfb8d8aff368f9a617f8c8a 100644 (file)
@@ -77,6 +77,7 @@ int hantro_get_format_depth(u32 fourcc)
        switch (fourcc) {
        case V4L2_PIX_FMT_P010:
        case V4L2_PIX_FMT_P010_4L4:
+       case V4L2_PIX_FMT_NV15:
        case V4L2_PIX_FMT_NV15_4L4:
                return 10;
        default:
index 69b5d9e12926fb408c08f8ba2139d05ba44389b7..e4703bb6be7c175a89c0b8868cf2eafb84a872ed 100644 (file)
@@ -2202,6 +2202,10 @@ static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx)
        case V4L2_PIX_FMT_NV12:
                hantro_reg_write(vpu, &av1_pp_out_format, 3);
                break;
+       case V4L2_PIX_FMT_NV15:
+               /* this mapping is RK specific */
+               hantro_reg_write(vpu, &av1_pp_out_format, 10);
+               break;
        default:
                hantro_reg_write(vpu, &av1_pp_out_format, 0);
        }
index b64f0658f7f1e77b3efd960b35cd54dec4edf4ef..acd29fa41d2d10af7803fe145c39ffb5f7267157 100644 (file)
@@ -92,6 +92,20 @@ static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
                        .step_height = MB_DIM,
                },
        },
+       {
+               .fourcc = V4L2_PIX_FMT_NV15,
+               .codec_mode = HANTRO_MODE_NONE,
+               .match_depth = true,
+               .postprocessed = true,
+               .frmsize = {
+                       .min_width = ROCKCHIP_VPU981_MIN_SIZE,
+                       .max_width = FMT_4K_WIDTH,
+                       .step_width = MB_DIM,
+                       .min_height = ROCKCHIP_VPU981_MIN_SIZE,
+                       .max_height = FMT_4K_HEIGHT,
+                       .step_height = MB_DIM,
+               },
+       },
        {
                .fourcc = V4L2_PIX_FMT_P010,
                .codec_mode = HANTRO_MODE_NONE,