net: dsa: bcm_sf2: force pause link settings

commit 7c97bc0128b2eecc703106112679a69d446d1a12 upstream.

The pause settings reported by the PHY should also be applied to the GMII port
status override otherwise the switch will not generate pause frames towards the
link partner despite the advertisement saying otherwise.

Fixes: 246d7f773c13 ("net: dsa: add Broadcom SF2 switch driver")
Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20220623030204.1966851-1-f.fainelli@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 11a72c4cbb9284e246e8ad08b1af4b79f1b42bd4..2279e5e2deeee0d500d877472c7b1c4a806bea10 100644 (file)
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -625,7 +625,9 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
        struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
        struct ethtool_eee *p = &priv->port_sts[port].eee;
        u32 id_mode_dis = 0, port_mode;
+       u16 lcl_adv = 0, rmt_adv = 0;
        const char *str = NULL;
+       u8 flowctrl = 0;
        u32 reg, offset;
 
        if (priv->type == BCM7445_DEVICE_ID)
@@ -697,10 +699,27 @@ force_link:
                break;
        }
 
+       if (phydev->duplex == DUPLEX_FULL &&
+           phydev->autoneg == AUTONEG_ENABLE) {
+               if (phydev->pause)
+                       rmt_adv = LPA_PAUSE_CAP;
+               if (phydev->asym_pause)
+                       rmt_adv |= LPA_PAUSE_ASYM;
+               if (phydev->advertising & ADVERTISED_Pause)
+                       lcl_adv = ADVERTISE_PAUSE_CAP;
+               if (phydev->advertising & ADVERTISED_Asym_Pause)
+                       lcl_adv |= ADVERTISE_PAUSE_ASYM;
+               flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+       }
+
        if (phydev->link)
                reg |= LINK_STS;
        if (phydev->duplex == DUPLEX_FULL)
                reg |= DUPLX_MODE;
+       if (flowctrl & FLOW_CTRL_TX)
+               reg |= TXFLOW_CNTL;
+       if (flowctrl & FLOW_CTRL_RX)
+               reg |= RXFLOW_CNTL;
 
        core_writel(priv, reg, offset);