arm64: dts: qcom: sm8750: Fix cluster hierarchy for idle states

SM8750 have two different clusters. cluster0 have CPU 0-5 as child and
cluster1 have CPU 6-7 as child. Each cluster requires its own idle state
and power domain in order to achieve complete domain sleep state.

However only single cluster idle state is added mapping CPU 0-7 to the
same power domain. Fix this by correctly mapping each CPU to respective
cluster power domain and make cluster1 power domain use same domain idle
state as cluster0 since both use same idle state parameters.

Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250226-sm8750_cluster_idle-v2-1-ef0ac81e242f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 798e1cf0bc96687f4cd9e9dd50627b5887994cee..735e7628df96e7d551fa575e566d3c5eb3ecb0f4 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -236,53 +236,59 @@
 
                cpu_pd0: power-domain-cpu0 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd1: power-domain-cpu1 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd2: power-domain-cpu2 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd3: power-domain-cpu3 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd4: power-domain-cpu4 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd5: power-domain-cpu5 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster0_pd>;
                        domain-idle-states = <&cluster0_c4>;
                };
 
                cpu_pd6: power-domain-cpu6 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster1_pd>;
                        domain-idle-states = <&cluster1_c4>;
                };
 
                cpu_pd7: power-domain-cpu7 {
                        #power-domain-cells = <0>;
-                       power-domains = <&cluster_pd>;
+                       power-domains = <&cluster1_pd>;
                        domain-idle-states = <&cluster1_c4>;
                };
 
-               cluster_pd: power-domain-cluster {
+               cluster0_pd: power-domain-cluster0 {
+                       #power-domain-cells = <0>;
+                       domain-idle-states = <&cluster_cl5>;
+                       power-domains = <&system_pd>;
+               };
+
+               cluster1_pd: power-domain-cluster1 {
                        #power-domain-cells = <0>;
                        domain-idle-states = <&cluster_cl5>;
                        power-domains = <&system_pd>;