pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks

Refactor the existing platform specific suspend/resume callback
so that each SoC variant has it's own callback containing the
SoC specific logic.

This allows exynosautov920 to have a dedicated function for using
eint_con_offset and eint_mask_offset. Also it is easily extendable
for gs101 which will need dedicated logic for handling the varying
register offset of fltcon0 via eint_fltcon_offset.

Reviewed-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-2-78ce0d4eb30c@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index dd07720e32cc09ea1d5a20c8d1cbea3bcff79204..4b5d4e436a337ff13dee6ef740a1500eaf86cc12 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -1419,8 +1419,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
                .pin_banks      = exynosautov920_pin_banks0,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks0),
                .eint_wkup_init = exynos_eint_wkup_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
                .retention_data = &exynosautov920_retention_data,
        }, {
                /* pin-controller instance 1 AUD data */
@@ -1431,43 +1431,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
                .pin_banks      = exynosautov920_pin_banks2,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks2),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        }, {
                /* pin-controller instance 3 HSI1 data */
                .pin_banks      = exynosautov920_pin_banks3,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks3),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        }, {
                /* pin-controller instance 4 HSI2 data */
                .pin_banks      = exynosautov920_pin_banks4,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks4),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        }, {
                /* pin-controller instance 5 HSI2UFS data */
                .pin_banks      = exynosautov920_pin_banks5,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks5),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        }, {
                /* pin-controller instance 6 PERIC0 data */
                .pin_banks      = exynosautov920_pin_banks6,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks6),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        }, {
                /* pin-controller instance 7 PERIC1 data */
                .pin_banks      = exynosautov920_pin_banks7,
                .nr_banks       = ARRAY_SIZE(exynosautov920_pin_banks7),
                .eint_gpio_init = exynos_eint_gpio_init,
-               .suspend        = exynos_pinctrl_suspend,
-               .resume         = exynos_pinctrl_resume,
+               .suspend        = exynosautov920_pinctrl_suspend,
+               .resume         = exynosautov920_pinctrl_resume,
        },
 };
 

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index ae82f42be83cf0a294452d7f44cd744295bb0408..18c327f7e313355c4aba72f49a79b1697244f1ba 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -762,105 +762,115 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
        return 0;
 }
 
-static void exynos_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
+static void exynos_set_wakeup(struct samsung_pin_bank *bank)
 {
-       struct exynos_eint_gpio_save *save = bank->soc_priv;
-       const void __iomem *regs = bank->eint_base;
+       struct exynos_irq_chip *irq_chip;
 
-       save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
-                                               + bank->eint_offset);
-       save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                                               + 2 * bank->eint_offset);
-       save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                                               + 2 * bank->eint_offset + 4);
-       save->eint_mask = readl(regs + bank->irq_chip->eint_mask
-                                               + bank->eint_offset);
-
-       pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
-       pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
-       pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
-       pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
+       if (bank->irq_chip) {
+               irq_chip = bank->irq_chip;
+               irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
+       }
 }
 
-static void exynosauto_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
+void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
 {
        struct exynos_eint_gpio_save *save = bank->soc_priv;
        const void __iomem *regs = bank->eint_base;
 
-       save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
-       save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
-
-       pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
-       pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);
+       if (bank->eint_type == EINT_TYPE_GPIO) {
+               save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                                      + bank->eint_offset);
+               save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                          + 2 * bank->eint_offset);
+               save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                          + 2 * bank->eint_offset + 4);
+               save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+                                       + bank->eint_offset);
+
+               pr_debug("%s: save     con %#010x\n",
+                        bank->name, save->eint_con);
+               pr_debug("%s: save fltcon0 %#010x\n",
+                        bank->name, save->eint_fltcon0);
+               pr_debug("%s: save fltcon1 %#010x\n",
+                        bank->name, save->eint_fltcon1);
+               pr_debug("%s: save    mask %#010x\n",
+                        bank->name, save->eint_mask);
+       } else if (bank->eint_type == EINT_TYPE_WKUP) {
+               exynos_set_wakeup(bank);
+       }
 }
 
-void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
+void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
 {
-       struct exynos_irq_chip *irq_chip = NULL;
+       struct exynos_eint_gpio_save *save = bank->soc_priv;
+       const void __iomem *regs = bank->eint_base;
 
        if (bank->eint_type == EINT_TYPE_GPIO) {
-               if (bank->eint_con_offset)
-                       exynosauto_pinctrl_suspend_bank(bank);
-               else
-                       exynos_pinctrl_suspend_bank(bank);
+               save->eint_con = readl(regs + bank->pctl_offset +
+                                      bank->eint_con_offset);
+               save->eint_mask = readl(regs + bank->pctl_offset +
+                                       bank->eint_mask_offset);
+               pr_debug("%s: save     con %#010x\n",
+                        bank->name, save->eint_con);
+               pr_debug("%s: save    mask %#010x\n",
+                        bank->name, save->eint_mask);
        } else if (bank->eint_type == EINT_TYPE_WKUP) {
-               if (!irq_chip) {
-                       irq_chip = bank->irq_chip;
-                       irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
-               }
+               exynos_set_wakeup(bank);
        }
 }
 
-static void exynos_pinctrl_resume_bank(struct samsung_pin_bank *bank)
+void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
 {
        struct exynos_eint_gpio_save *save = bank->soc_priv;
        void __iomem *regs = bank->eint_base;
 
-       pr_debug("%s:     con %#010x => %#010x\n", bank->name,
-                       readl(regs + EXYNOS_GPIO_ECON_OFFSET
-                       + bank->eint_offset), save->eint_con);
-       pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
-                       readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                       + 2 * bank->eint_offset), save->eint_fltcon0);
-       pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
-                       readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                       + 2 * bank->eint_offset + 4), save->eint_fltcon1);
-       pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
-                       readl(regs + bank->irq_chip->eint_mask
-                       + bank->eint_offset), save->eint_mask);
-
-       writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
-                                               + bank->eint_offset);
-       writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                                               + 2 * bank->eint_offset);
-       writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
-                                               + 2 * bank->eint_offset + 4);
-       writel(save->eint_mask, regs + bank->irq_chip->eint_mask
-                                               + bank->eint_offset);
+       if (bank->eint_type == EINT_TYPE_GPIO) {
+               pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                              + bank->eint_offset), save->eint_con);
+               pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                              + 2 * bank->eint_offset), save->eint_fltcon0);
+               pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                              + 2 * bank->eint_offset + 4),
+                        save->eint_fltcon1);
+               pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
+                        readl(regs + bank->irq_chip->eint_mask
+                              + bank->eint_offset), save->eint_mask);
+
+               writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+                      + bank->eint_offset);
+               writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                      + 2 * bank->eint_offset);
+               writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                      + 2 * bank->eint_offset + 4);
+               writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+                      + bank->eint_offset);
+       }
 }
 
-static void exynosauto_pinctrl_resume_bank(struct samsung_pin_bank *bank)
+void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
 {
        struct exynos_eint_gpio_save *save = bank->soc_priv;
        void __iomem *regs = bank->eint_base;
 
-       pr_debug("%s:     con %#010x => %#010x\n", bank->name,
-                readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
-       pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
-                readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
-
-       writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
-       writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
-
-}
-
-void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
-{
        if (bank->eint_type == EINT_TYPE_GPIO) {
-               if (bank->eint_con_offset)
-                       exynosauto_pinctrl_resume_bank(bank);
-               else
-                       exynos_pinctrl_resume_bank(bank);
+               /* exynosautov920 has eint_con_offset for all but one bank */
+               if (!bank->eint_con_offset)
+                       exynos_pinctrl_resume(bank);
+
+               pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+                        readl(regs + bank->pctl_offset + bank->eint_con_offset),
+                        save->eint_con);
+               pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
+                        readl(regs + bank->pctl_offset +
+                              bank->eint_mask_offset), save->eint_mask);
+
+               writel(save->eint_con,
+                      regs + bank->pctl_offset + bank->eint_con_offset);
+               writel(save->eint_mask,
+                      regs + bank->pctl_offset + bank->eint_mask_offset);
        }
 }
 

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 341155c1abd153eb3efec5212b268ccfa535bd8e..3a771862b4b1762b32f9e067b011e80cfebb99d2 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -240,6 +240,8 @@ struct exynos_muxed_weint_data {
 
 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
+void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
+void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
 void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
 void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
 struct samsung_retention_ctrl *