spi: sophgo: Fix incorrect use of bus width value macros

[ Upstream commit d9813cd23d5a7b254cc1b1c1ea042634d8da62e6 ]

The previous code initialized the 'reg' value with specific bus-width
values (BUS_WIDTH_2_BIT and BUS_WIDTH_4_BIT), which introduces ambiguity.
Replace them with BUS_WIDTH_MASK to express the intention clearly.

Fixes: de16c322eefb ("spi: sophgo: add SG2044 SPI NOR controller driver")
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://patch.msgid.link/20251117090559.78288-1-looong.bin@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/spi-sg2044-nor.c b/drivers/spi/spi-sg2044-nor.c
index af48b1fcda930f3cd0bdd57d80e076918d94010d..37f1cfe10be460574f59d8765af4f9588bfda373 100644 (file)
--- a/drivers/spi/spi-sg2044-nor.c
+++ b/drivers/spi/spi-sg2044-nor.c
@@ -42,6 +42,7 @@
 #define SPIFMC_TRAN_CSR_TRAN_MODE_RX           BIT(0)
 #define SPIFMC_TRAN_CSR_TRAN_MODE_TX           BIT(1)
 #define SPIFMC_TRAN_CSR_FAST_MODE              BIT(3)
+#define SPIFMC_TRAN_CSR_BUS_WIDTH_MASK         GENMASK(5, 4)
 #define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT                (0x00 << 4)
 #define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT                (0x01 << 4)
 #define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT                (0x02 << 4)
@@ -122,8 +123,7 @@ static u32 sg2044_spifmc_init_reg(struct sg2044_spifmc *spifmc)
        reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
        reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK |
                 SPIFMC_TRAN_CSR_FAST_MODE |
-                SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT |
-                SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT |
+                SPIFMC_TRAN_CSR_BUS_WIDTH_MASK |
                 SPIFMC_TRAN_CSR_DMA_EN |
                 SPIFMC_TRAN_CSR_ADDR_BYTES_MASK |
                 SPIFMC_TRAN_CSR_WITH_CMD |