drm/xe: Move CCS enablement to engine setup RTP

Most register programming for engine setup happens via RTP tables in
hw_engine_setup_default_state().  Move the programming of RCU_MODE[0]
which enables the platform's CCS engine(s) there.  This both makes the
code more consistent (other RCU_MODE register programming is already
happening in this RTP table) and improves debuggability (since RTP
contents and checks of their correct programming are exposed via
debugfs).  It also helps consolidate the regular driver initialization
paths with the vestigial and currently unused execlist (i.e., non-GuC)
initialization.

With the original programming, the RCU_MODE register (which is a single
global register, not a per-engine register) was getting re-programmed
with the same value during the initialization of each CCS engine.  When
moved to the RTP table, we use the xe_rtp_match_first_render_or_compute
match function so that it will just be programmed once, while doing the
initialization for the first RCS/CCS engine, which avoids the redundant
and unnecessary repetition.

We can also safely drop the explicit addition of RCU_MODE from the GuC
ADS save-restore list now since all registers programmed via RTP tables
are automatically added to the GuC's list.

v2:
 - Only enable CCS engines on Xe_HP and later.  Even though Xe_LP
   platforms technically have a CCS engine, it's never been enabled on
   i915 or Xe due to other issues on these old platforms.

Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260424-engine-setup-v2-1-59cc620a25f1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 755a2bff5d7bc65d68f120cb4c7cecbbd0c3a297..9d158a448a9968546032b20efb02cddb760ffc7f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -59,10 +59,6 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
                lrc_desc |= FIELD_PREP(SW_CTX_ID, ctx_id);
        }
 
-       if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
-               xe_mmio_write32(mmio, RCU_MODE,
-                               REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE));
-
        xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
        lrc->ring.old_tail = lrc->ring.tail;
 

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 92c6981fe22030d8be13444f53206438a493886a..d0497d9f43a28d31d642e2fd16da71cb849477df 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -748,7 +748,6 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
                { .reg = RING_MODE(hwe->mmio_base),                     },
                { .reg = RING_HWS_PGA(hwe->mmio_base),                  },
                { .reg = RING_IMR(hwe->mmio_base),                      },
-               { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain  },
                { .reg = CCS_MODE,
                  .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) },
        };

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 2f9c1c063f16c7ced090c944144fdd2a9623e97e..74f29025dd6cacaf2bc420f45c8dec4037c589b9 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -325,14 +325,8 @@ u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
 
 void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
 {
-       u32 ccs_mask =
-               xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
        u32 ring_mode = REG_MASKED_FIELD_ENABLE(GFX_DISABLE_LEGACY_MODE);
 
-       if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
-               xe_mmio_write32(&hwe->gt->mmio, RCU_MODE,
-                               REG_MASKED_FIELD_ENABLE(RCU_MODE_CCS_ENABLE));
-
        xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
        xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
                                  xe_bo_ggtt_addr(hwe->hwsp));
@@ -465,6 +459,11 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
                  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
                                     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
                },
+               { XE_RTP_NAME("Enable CCS Engine(s)"),
+                 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
+                              FUNC(xe_rtp_match_first_render_or_compute)),
+                 XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
+               },
                /* Use Fixed slice CCS mode */
                { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
                  XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),