drm/i915/lt_phy: Add check if PLL is enabled

Add check for PLL enabling and return early if
PLL is not enabled.

v2: Use PCLK PLL ACK bit to check if PLL is enabled (Suraj)
v3: Check only if PCLK PLL ACK bit for lane 0 is enabled (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-3-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index f768804122c1c6cf5701f649ca69de9754a7cbb8..e1c95f58b6ae628446e6d71b21e94fe94bb8e73f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2176,6 +2176,14 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
        return false;
 }
 
+static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
+{
+       struct intel_display *display = to_intel_display(encoder);
+
+       return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
+                            XELPDP_LANE_PCLK_PLL_ACK(0);
+}
+
 void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
                                       const struct intel_crtc_state *crtc_state,
                                       struct intel_lt_phy_pll_state *pll_state)
@@ -2185,6 +2193,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
        struct ref_tracker *wakeref;
        int i, j, k;
 
+       if (!intel_lt_phy_pll_is_enabled(encoder))
+               return;
+
        pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
        if (pll_state->tbt_mode)
                return;