drm/i915/dp: Factor out intel_dp_link_bw_overhead()

Factor out intel_dp_link_bw_overhead(), used later for BW calculation
during DP SST mode validation and state computation.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-7-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e687d61ff49c38e29994ec8694dee0340e261f3b..a8d08e4f8137c7b5120e17a10844b8d99e61b3af 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -424,6 +424,32 @@ static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
        return 1;
 }
 
+int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay,
+                             int dsc_slice_count, int bpp_x16, unsigned long flags)
+{
+       int overhead;
+
+       WARN_ON(flags & ~(DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK |
+                         DRM_DP_BW_OVERHEAD_FEC));
+
+       if (drm_dp_is_uhbr_rate(link_clock))
+               flags |= DRM_DP_BW_OVERHEAD_UHBR;
+
+       if (dsc_slice_count)
+               flags |= DRM_DP_BW_OVERHEAD_DSC;
+
+       overhead = drm_dp_bw_overhead(lane_count, hdisplay,
+                                     dsc_slice_count,
+                                     bpp_x16,
+                                     flags);
+
+       /*
+        * TODO: clarify whether a minimum required by the fixed FEC overhead
+        * in the bspec audio programming sequence is required here.
+        */
+       return max(overhead, intel_dp_bw_fec_overhead(flags & DRM_DP_BW_OVERHEAD_FEC));
+}
+
 /*
  * The required data bandwidth for a mode with given pixel clock and bpp. This
  * is the required net bandwidth independent of the data bandwidth efficiency.

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 97e361458f7608e692891907e0a54e612704524a..d7f9410129f49df37d77399bcc037991a56bea3e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -117,6 +117,8 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 bool intel_dp_source_supports_tps3(struct intel_display *display);
 bool intel_dp_source_supports_tps4(struct intel_display *display);
 
+int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay,
+                             int dsc_slice_count, int bpp_x16, unsigned long flags);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
                                 int bw_overhead);

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1a4784f0cd6bd2dbdeb2bf16dd2012e9e19647d9..c1058b4a85d0230781979b13aefa3ff104bbec7f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -180,26 +180,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
        const struct drm_display_mode *adjusted_mode =
                &crtc_state->hw.adjusted_mode;
        unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
-       int overhead;
 
-       flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
        flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
        flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
 
-       if (dsc_slice_count)
-               flags |= DRM_DP_BW_OVERHEAD_DSC;
-
-       overhead = drm_dp_bw_overhead(crtc_state->lane_count,
-                                     adjusted_mode->hdisplay,
-                                     dsc_slice_count,
-                                     bpp_x16,
-                                     flags);
-
-       /*
-        * TODO: clarify whether a minimum required by the fixed FEC overhead
-        * in the bspec audio programming sequence is required here.
-        */
-       return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
+       return intel_dp_link_bw_overhead(crtc_state->port_clock,
+                                        crtc_state->lane_count,
+                                        adjusted_mode->hdisplay,
+                                        dsc_slice_count,
+                                        bpp_x16,
+                                        flags);
 }
 
 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,